Asynchronous Sequential Circuits
Asynchronous Sequential Circuits
Circuits
Asynch. vs. Synch.
Asynchronous circuits dont use
clock pulses
State transitions by changes in inputs
Storage Elements:
Clockless storage elements or
Delay elements
In many cases, as combinational
feedback
Normally much harder to design
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Asynch. Sequential Circuit
x1 z1
x2 z2
inputs outputs
Combinational
xn zm
Circuit
y1 Y1
y2 Y2 Next
Current
State
State yk Yk
delay
delay
delay
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Asynch. Sequential Circuit
yi = Yi in steady state (but may be
different during transition)
Simultaneous change in two (or
more) inputs is prohibited.
The time between two changes must
be less than the time of stability.
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Advantages and Disadvantages
Advantages:
Low power
High performance
No need for clock
Disadvantages:
Complexity of design process
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Analysis
y1
x Y1
y2
Y2
00 0 0 00 0 1 00 00 01
01 1 0 01 1 1 01 11 01
11 1 1 11 1 0 11 11 10
10 0 1 10 0 0 10 00 10
00 00 01
01 11 01
(Transition Table) Y1 Y2
11 11 10
10 00 10
At y1y2x = 000, if x: 0 1
then Y1Y2: 00 01
then y1y2 = 01 (2nd row): stable
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Analysis
In general, if an input takes the circuit to
an unstable state, yis change until a
stable state is found.
x
y1 y2 0 1
00 00 01
01 11 01
General state of circuit:
11 11 10
y1y2x:
There are 4 stable states: 10 00 10
00 00 01
01 11 01
10 00 10
11 11 10
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Flow Table
As Transition Table (but with symbolic states):
x
0 1
a a b
b c b
c c d
d a d
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Flow Table: Example 2
Two states, two inputs, one output.
x1 x2
00 01 11 10
a a ,0 a ,0 a ,0 b ,0
b a ,0 a ,0 b ,1 b ,0
b a ,0 a ,0 b ,1 b ,0 1 0 ,0 0 ,0 1 ,1 1 ,0
x1 x2 x1 x2
00 01 11 10 00 01 11 10
y y
0 0 0 0 1 0 0 0 0 0
1 0 0 1 1 1 0 0 1 0
z = x1x2y
x1
x2 Y
Y = x1x2+x1y
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Race Condition
If two (or more) state variables
change in response to a change in
an input, there is a race condition.
E.g. from 00 to 11, due to delays
00 01 11 OR
00 10 11.
Critical Race:
If final steady state depends on the
order of changes in state vars.
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Race: Examples
Noncritical Cases:
x x
y 1y 2 0 1
y1y2 0 1
00 00 11 00 00 11
01 11 01 01
11 11 11 01
10 11 10 11
00 11 00 11 01
00 01 11 00 01
00 10 11 00 10 11 01
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Race: Examples
Critical Cases:
x x
y 1y 2 0 1
y1y2 0 1
00 00 11 00 00 11
01 11 01 01
11 11 11 11
10 10 10 10
00 11 00 11
00 01 11 00 01
00 10 00 10
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Instability
x1 Y
x2 Y = (x1 y) x2
x1 x2
00 01 11 10
y
0 0 1 1 0
For x1x2 = 11, there is no steady state.
Oscillation.
1 0 1 0 0
For x1x2 = 11, Y = y unstable.
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THE END
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No-Race State Assignment
Must assign binary values to states such that:
one change in an input may not cause two changes in state variables.
because, due to delays, one of the variable change sooner and may stay in
an unwanted stable state.
From a, if x1x2 = 10 11, must go to c and stay there.
But by the following assignment, it may go to b and stay there.
x1 x2
00 01
00 01 11 10
a b
a a b c a
b a b b c
c a c c c c
11
a and b must be different in one bit,
a and c must be different in one bit.
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No-Race State Assignment
Impossible add one more row.
x1 x2
00 01 11 10
a a b d a
b a b b c
00 01
c d c c c a b
d a - c -
d is an intermediate c
(unstable) state.
d
10 11
- means any value can be
assigned (Except d=10).
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Example 2
x1 x2
00 01 11 10
00 01
a b a d a
a b
b b d b a
c c a b c
d c d d c d c
10 11
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Example 2 y1 y2
x1 x2 00 01 11 10
00 01 11 10 y3
0 a b c g
a = 000 b a e a
1 e d f 0
b = 001 b d b a
c = 011 c g b c b is adjacent to a, c, d
c a through g
g = 010 - a - -
a d through e
110 - - - - d c through f
00 01
f = 111 c - - c
a b
d = 101 f d d f
e = 100 - - d -
d c
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10 11