Introduction to

CMOS VLSI
Design

Lecture 17:
Design for Testability
David Harris

Harvey Mudd College

Spring 2004
 Outline
Testing
Logic Verification
Silicon Debug
Manufacturing Test
Fault Models
Observability and Controllability
Design for Test
Scan
BIST
Boundary Scan

17: Design for Testability CMOS VLSI Design Slide 2

 Testing
Testing is one of the most expensive parts of chips
Logic verification accounts for > 50% of design
effort for many chips
Debug time after fabrication has enormous
opportunity cost
Shipping defective parts can sink a company

Example: Intel FDIV bug

Logic error not caught until > 1M units shipped
Recall cost $450M (!!!)

17: Design for Testability CMOS VLSI Design Slide 3

 Logic Verification
Does the chip simulate correctly?
Usually done at HDL level
Verification engineers write test bench for HDL
Cant test all cases
Look for corner cases
Try to break logic design
Ex: 32-bit adder
Test all combinations of corner cases as inputs:
0, 1, 2, 231-1, -1, -231, a few random numbers
Good tests require ingenuity

17: Design for Testability CMOS VLSI Design Slide 4

 Silicon Debug
Test the first chips back from fabrication
If you are lucky, they work the first time
If not
Logic bugs vs. electrical failures
Most chip failures are logic bugs from inadequate
simulation
Some are electrical failures
Crosstalk
Dynamic nodes: leakage, charge sharing
Ratio failures
A few are tool or methodology failures (e.g. DRC)
Fix the bugs and fabricate a corrected chip

17: Design for Testability CMOS VLSI Design Slide 5

 Shmoo Plots
How to diagnose failures?
Hard to access chips
Picoprobes
Electron beam
Laser voltage probing
Built-in self-test
Shmoo plots
Vary voltage, frequency
Look for cause of
electrical failures
17: Design for Testability CMOS VLSI Design Slide 6
 Shmoo Plots

DFF/latch Initialization failures,

operates faster as different behaviors at diff voltages.
voltage goes up
17: Design for Testability CMOS VLSI Design Slide 7
 Shmoo Plots

At a particular frequency,
Leakage problem with dynamic
aggressor and victim waveforms
logic.
align, so failure.

17: Design for Testability CMOS VLSI Design Slide 8

 Shmoo Plots

Race condition at certain Weakly-held node leaks worse

voltage giving a hold time at higher voltages
failure.

17: Design for Testability CMOS VLSI Design Slide 9

 Shmoo Plots
How to diagnose failures?
Hard to access chips
Picoprobes
Electron beam
Laser voltage probing
Built-in self-test
Shmoo plots
Vary voltage, frequency
Look for cause of
electrical failures
17: Design for Testability CMOS VLSI Design Slide 10
 Manufacturing Test
A speck of dust on a wafer is sufficient to kill chip
Yield of any chip is < 100%
Must test chips after manufacturing before
delivery to customers to only ship good parts
Manufacturing testers are
very expensive
Minimize time on tester
Careful selection of
test vectors

17: Design for Testability CMOS VLSI Design Slide 11

 Testing Your Chips
If you dont have a multimillion dollar tester:
Build a breadboard with LEDs and switches
Hook up a logic analyzer and pattern generator
Or use a low-cost functional chip tester

17: Design for Testability CMOS VLSI Design Slide 12

 TestosterICs
Ex: TestosterICs functional chip tester
Designed by clinic teams and David Diaz at HMC
Reads your IRSIM test vectors, applies them to
your chip, and reports assertion failures

17: Design for Testability CMOS VLSI Design Slide 13

 Stuck-At Faults
How does a chip fail?
Usually failures are shorts between two
conductors or opens in a conductor
This can cause very complicated behavior
A simpler model: Stuck-At
Assume all failures cause nodes to be stuck-at
0 or 1, i.e. shorted to GND or VDD
Not quite true, but works well in practice

17: Design for Testability CMOS VLSI Design Slide 14

 Examples

Stuck at 1

Stuck at 0

17: Design for Testability CMOS VLSI Design Slide 15

Observability & Controllability
Observability: ease of observing a node by watching
external output pins of the chip
Controllability: ease of forcing a node to 0 or 1 by
driving input pins of the chip

Combinational logic is usually easy to observe and

control
Finite state machines can be very difficult, requiring
many cycles to enter desired state
Especially if state transition diagram is not known
to the test engineer
17: Design for Testability CMOS VLSI Design Slide 16
 Test Pattern Generation
Manufacturing test ideally would check every node in
the circuit to prove it is not stuck.
Apply the smallest sequence of test vectors
necessary to prove each node is not stuck.

Good observability and controllability reduces

number of test vectors required for manufacturing
test.
Reduces the cost of testing
Motivates design-for-test

17: Design for Testability CMOS VLSI Design Slide 17

 Test Example
SA1 SA0 A3 n1
A2
A3 Y

A2 A1
n2 n3

A0
A1
A0
n1
n2
n3
Y

Minimum set:
17: Design for Testability CMOS VLSI Design Slide 18
 Test Example
SA1 SA0 A3 n1
A2
A3 {0110} {1110} Y

A2 A1
n2 n3

A0
A1
A0
n1
n2
n3
Y

Minimum set:
17: Design for Testability CMOS VLSI Design Slide 19
 Test Example
SA1 SA0 A3 n1
A2
A3 {0110} {1110} Y

A2 {1010}{1110} A1
n2 n3

A0
A1
A0
n1
n2
n3
Y

Minimum set:
17: Design for Testability CMOS VLSI Design Slide 20
 Test Example
SA1 SA0 A3 n1
A2
A3 {0110} {1110} Y

A2 {1010}{1110} A1
n2 n3

A0
A1 {0100}{0110}
A0
n1
n2
n3
Y

Minimum set:
17: Design for Testability CMOS VLSI Design Slide 21
 Test Example
SA1 SA0 A3 n1
A2
A3 {0110} {1110} Y

A2 {1010}{1110} A1
n2 n3

A0
A1 {0100}{0110}
A0 {0110} {0111}
n1
n2
n3
Y

Minimum set:
17: Design for Testability CMOS VLSI Design Slide 22
 Test Example
SA1 SA0 A3 n1
A2
A3 {0110} {1110} Y

A2 {1010}{1110} A1
n2 n3

A0
A1 {0100}{0110}
A0 {0110} {0111}
n1 {1110} {0110}
n2
n3
Y

Minimum set:
17: Design for Testability CMOS VLSI Design Slide 23
 Test Example
SA1 SA0 A3 n1
A2
A3 {0110} {1110} Y

A2 {1010}{1110} A1
n2 n3

A0
A1 {0100}{0110}
A0 {0110} {0111}
n1 {1110} {0110}
n2 {0110} {0100}
n3
Y

Minimum set:
17: Design for Testability CMOS VLSI Design Slide 24
 Test Example
SA1 SA0 A3 n1
A2
A3 {0110} {1110} Y

A2 {1010}{1110} A1
n2 n3

A0
A1 {0100}{0110}
A0 {0110} {0111}
n1 {1110} {0110}
n2 {0110} {0100}
n3 {0101}{0110}
Y

Minimum set:
17: Design for Testability CMOS VLSI Design Slide 25
 Test Example
SA1 SA0 A3 n1
A2
A3 {0110} {1110} Y

A2 {1010}{1110} A1
n2 n3

A0
A1 {0100}{0110}
A0 {0110} {0111}
n1 {1110} {0110}
n2 {0110} {0100}
n3 {0101}{0110}
Y {0110} {1110}

Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}

17: Design for Testability CMOS VLSI Design Slide 26
 Design for Test
Design the chip to increase observability and
controllability

If each register could be observed and controlled,

test problem reduces to testing combinational logic
between registers.

Better yet, logic blocks could enter test mode where

they generate test patterns and report the results
automatically.

17: Design for Testability CMOS VLSI Design Slide 27

 Scan
Convert each flip-flop to a scan register SCAN CLK

Only costs one extra multiplexer

Flop
SI Q
D
Normal mode: flip-flops behave as usual
Scan mode: flip-flops behave as shift register
scan-in

Flop

Flop

Flop
Contents of flops
can be scanned
Flop

Flop

Flop
Logic Logic
inputs Cloud Cloud outputs

out and new

Flop

Flop

Flop
values scanned
Flop

Flop

Flop
in scanout

17: Design for Testability CMOS VLSI Design Slide 28

 Scannable Flip-flops
SCAN
SCAN CLK Q

D
D 0 Flop X
Q Q
SI 1 SI
(a)

(b)

D
Q
d
SCAN
d X
Q
s
s
SI
(c)
s

17: Design for Testability CMOS VLSI Design Slide 29

 Built-in Self-test
Built-in self-test lets blocks test themselves
Generate pseudo-random inputs to comb. logic
Combine outputs into a syndrome
With high probability, block is fault-free if it
produces the expected syndrome

17: Design for Testability CMOS VLSI Design Slide 30

 PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D
1
2
3
4
5
6
7

17: Design for Testability CMOS VLSI Design Slide 31

 PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D
1 110
2
3
4
5
6
7

17: Design for Testability CMOS VLSI Design Slide 32

 PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D
1 110
2 101
3
4
5
6
7

17: Design for Testability CMOS VLSI Design Slide 33

 PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D
1 110
2 101
3 010
4
5
6
7

17: Design for Testability CMOS VLSI Design Slide 34

 PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D
1 110
2 101
3 010
4 100
5
6
7

17: Design for Testability CMOS VLSI Design Slide 35

 PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D
1 110
2 101
3 010
4 100
5 001
6
7

17: Design for Testability CMOS VLSI Design Slide 36

 PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D
1 110
2 101
3 010
4 100
5 001
6 011
7

17: Design for Testability CMOS VLSI Design Slide 37

 PRSG
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
CLK
0 111
Q[0] Q[1] Q[2]
Flop

Flop

Flop
D D D
1 110
2 101
3 010
4 100
5 001
6 011
7 111 (repeats)

17: Design for Testability CMOS VLSI Design Slide 38

 BILBO
Built-in Logic Block Observer
Combine scan with PRSG & signature analysis
D[0] D[1] D[2]

C[0]
C[1]

Q[2] / SO
Flop

Flop

Flop
SI 1

0 Q[0]
Q[1]

MODE C[1] C[0]

Scan 0 0
Logic Signature
PRSG Test 0 1
Cloud Analyzer
Reset 1 0
Normal 1 1

17: Design for Testability CMOS VLSI Design Slide 39

 Boundary Scan
Testing boards is also difficult
Need to verify solder joints are good
Drive a pin to 0, then to 1
Check that all connected pins get the values
Through-hold boards used bed of nails
SMT and BGA boards cannot easily contact pins
Build capability of observing and controlling pins into
each chip to make board test easier

17: Design for Testability CMOS VLSI Design Slide 40

Boundary Scan Example
PackageInterconnect

CHIP B CHIP C

Serial Data Out

CHIP A CHIP D

IO pad and Boundary Scan

Cell

Serial Data In

17: Design for Testability CMOS VLSI Design Slide 41

 Boundary Scan
Interface
Boundary scan is accessed through five pins
TCK: test clock
TMS: test mode select
TDI: test data in
TDO: test data out
TRST*: test reset (optional)

Chips with internal scan chains can access the

chains through boundary scan for unified test
strategy.

17: Design for Testability CMOS VLSI Design Slide 42

 Summary
Think about testing from the beginning
Simulate as you go
Plan for test after fabrication

If you dont test it, it wont work! (Guaranteed)

17: Design for Testability CMOS VLSI Design Slide 43