Central Processing Unit

Lecture 22

Overview

Introduction
General Register Organization
Stack Organization
Instruction Formats
Addressing Modes
Data Transfer and Manipulation
Program Control and Program Interrupt
CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 22

Major Components of CPU

Storage Components
Registers
Flags

Execution (Processing) Components

Arithmetic Logic Unit(ALU)
Arithmetic calculations, Logical computations, Shifts/Rotates

Transfer Components
Bus

Control Components
Control Unit

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 22

Register

In Basic Computer, there is only one general purpose

register, the Accumulator (AC)
In modern CPUs, there are many general purpose
registers
It is advantageous to have many registers
Transfer between registers within the processor
are relatively fast
Going off the processor to access memory is
much slower
Important:
How many registers will be the best ?

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 22

General Register Organization

Input

Clock
R1
R2
R3
R4
R5
R6
R7
Load
(7 lines)

SELA

3x8
decoder

MUX

MUX

A bus

SELD
OPR

B bus

ALU

Output

CSE 211, Computer Organization and Architecture

}SELB

Central Processing Unit

Lecture 22

Operation of ControlUnit

The control unit

Directs the information flow through ALU by
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1 R2 + R3
[1] MUX A selector (SELA): BUS A R2
[2] MUX B selector (SELB): BUS B R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1 Out Bus
Control Word

3
SELA

3
SELB

3
SELD

Encoding of register selection fields

5
OPR

Binary
Code
000
001
010
011
100
101
110
111

SELA
Input
R1
R2
R3
R4
R5
R6
R7

CSE 211, Computer Organization and Architecture

SELB
Input
R1
R2
R3
R4
R5
R6
R7

SELD
None
R1
R2
R3
R4
R5
R6
R7

Central Processing Unit

Lecture 22

ALU Control

Encoding of ALU operations

OPR
Select
00000
00001
00010
00101
00110
01000
01010
01100
01110
10000
11000

Operation
Symbol
Transfer A
TSFA
Increment A
INCA
ADD A + B
ADD
Subtract A - B SUB
Decrement A DECA
AND A and B AND
OR A and B
OR
XOR A and B XOR
Complement A COMA
Shift right A
SHRA
Shift left A
SHLA

Examples of ALU Microoperations

Symbolic Designation
MicrooperationSELA SELB
R1 R2 R3
R4 R4 R5
R6 R6 + 1
R7 R1
Output R2
Output Input
R4 shl R4
R5 0

SELD OPR

R2
R4

R3
R5
R6

R1

R2
Input
R4
R5

CSE 211, Computer Organization and Architecture

R5

R1
R4

Control Word
SUB
OR

010 011 001 0

100 101 100 0
R6
INCA
11
R7
TSFA
001 000 111 0
None TSFA
010 000 00
None TSFA
000 000 00
R4
SHLA
10
R5
XOR
101 101 101 0

Central Processing Unit

Lecture 23

Stack Organization

Stack
Very useful feature for nested subroutines, nested

interrupt services
Also efficient for arithmetic expression evaluation
Storage which can be accessed in LIFO
Pointer: SP
Only PUSH and POP operations are applicable

Stack Organization
Register Stack Organization
Memory Stack Organization

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 23

Register Stack Organization

63

Flags
FULL

EMPTY

Stack pointer
SP

C
B
A

6 bits

Push, Pop operations

DR

/* Initially, SP = 0, EMPTY = 1, FULL = 0 */

PUSH
SP
SP + 1
M[SP]
DR
If (SP = 0) then (FULL
EMPTY
0

POP
1)

DR
M[SP]
SP
SP 1
If (SP = 0) then (EMPTY
FULL
0

CSE 211, Computer Organization and Architecture

1)

4
3
2
1
0

Central Processing Unit

Lecture 23

Memory Stack Organization

1000

Memory with Program, Data,

and Stack Segments

PC

Program
(instructions)

AR

Data
(operands)

SP

- A portion of memory is used as a

stack with a
processor register as a stack pointer

3000

stack
3997
3998
3999
4000
4001

SP SP - 1
M[SP] DR
- POP: DR M[SP]
SP SPdo
+1
- Most computers
not provide hardware to check stack
overflow (full
stack) or underflow (empty stack) must be done in
CSE 211, Computer Organization and Architecture
- PUSH:

Central Processing Unit

Lecture 23

10

Reverse Polish Notation

Arithmetic Expressions: A + B
A + B Infix notation
+ A B Prefix or Polish notation
A B + Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for
stack manipulation

Evaluation of Arithmetic Expressions

Any arithmetic expression can be expressed in

parenthesis-free Polish notation, including reverse Polish
notation
(3 * 4) + (5 * 6)

4
3

12

5
12

34*56*+

6
5
12

30
12

42

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 23

11

Processor Organization

In general, most processors are organized

in one of 3 ways
Single register (Accumulator) organization
Basic Computer is a good example
Accumulator is the only general purpose register

General register organization

Used by most modern computer processors
Any of the registers can be used as the source or
destination for computer operations

Stack organization
All operations are done using the hardware stack
CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 24

12

Instruction Format

Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a processor
register(s)
Mode field
- determines how the address field is to be
interpreted (to
get
effective
address
or the
operand) format
The number of
address
fields
in the
instruction

depends on the internal

organization of CPU
The three most common CPU organizations:
Single accumulator organization:
ADD X
/* AC AC + M[X] */
General register organization:
ADD R1, R2, R3
/* R1 R2 + R3 */
ADD R1, R2
/* R1 R1 + R2 */
MOV R1, R2
/* R1 R2 */
ADD R1, X
/* R1 R1 + M[X] */
Stack organization:
PUSH X
/* TOS M[X] */
ADD

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 24

13

Three & Two Address Instruction

Three-Address Instructions
*/
*/
*/

Program to evaluate X = (A + B) * (C + D) :
ADD R1, A, B
/*
R1 M[A] + M[B]
ADD R2, C, D
MUL X, R1, R2 /*

/*

R2 M[C] + M[D]

M[X] R1 * R2

- Results in short programs

- Instruction becomes long (many bits)

Two-Address Instructions

Program to evaluate X = (A + B) * (C + D) :

MOV R1, A
/* R1 M[A]
ADD
R1, B
/* R1 R1 + M[B]
MOV R2, C
/* R2 M[C]
ADD
R2, D
/* R2 R2 + M[D]
MUL
R1, R2
/* R1 R1 * R2
MOV
X, R1
/* M[X] R1
CSE 211, Computer Organization and Architecture

*/
*/
*/
*/
*/
*/

Central Processing Unit

Lecture 24

14

One Address Instruction

One-Address Instructions

- Use an implied AC register for all data manipula

- Program to evaluate X = (A + B) * (C + D) :
LOAD
A
/* AC M[A]
*/
ADD
B
/* AC AC + M[B]
*/
STORE T
/* M[T] AC
*/
LOAD
C
/* AC M[C]
*/
ADD
D
/* AC AC + M[D]
*/
CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 24

15

Zero Address Instruction

Zero-Address Instructions
- Can be found in a stack-organized computer
- Program to evaluate X = (A + B) * (C + D) :
PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
+ B) */
POP
X

/*
/*
/*
/*
/*
/*
/*
/*

TOS A */
TOS B */
TOS (A + B) */
TOS C */
TOS D */
TOS (C + D) */
TOS (C + D) * (A
M[X] TOS*/

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 25

16

Addressing Mode

Addressing Modes
- Specifies a rule for interpreting or modifying the address
field of the
instruction (before the operand is actually
referenced)
- Variety of addressing modes
- to give programming flexibility to the user
- toMode
use the bits in the address field of the
1. Implied
instruction
efficiently
- Address
of the operands are specified implicitly in the
definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP]
- Examples from Basic Computer - CLA, CME, INP

2. Immediate Mode
- Instead of specifying the address of the operand, operand
itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand
CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 25

17

Addressing Mode

3. Register Mode
- Address specified in the instruction is the register
address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory
addressing
- EA = IR(R) (IR(R): Register field of IR)

4. Register Indirect Mode

- Instruction specifies a register which contains the memory
address of the operand
- Saving instruction bits since register address is shorter
than the memory address
- Slower to acquire an operand than both the register
addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)

5. Autoincrement or Autodecrement Mode

- When the address in the register is used to access
CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 25

18

Addressing Mode

6. Direct Address Mode

- Instruction specifies the memory address which can be
used directly to access the
memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address for a
large physical memory space
- EA = IR(addr) (IR(addr): address field of IR)

7. Indirect Addressing Mode

- The address field of an instruction specifies the address of
a memory location that
contains the address of the
operand
- When the abbreviated address is used large physical
memory can be addressed
with a relatively small number of
bits
- Slow to acquire an operand because of an additional
memory access
CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 25

19

Addressing Mode

8. Relative Addressing Modes

- The Address fields of an instruction specifies the part of
the address (abbreviated
address) which can be used along
with a designated register to calculate the
address of the
operand
- Address field of the instruction is short
- Large physical memory can be accessed with a small
number of address bits
- EA = f(IR(address), R), R is sometimes implied
-3 different Relative Addressing Modes depending on R;

PC Relative Addressing Mode (R = PC)

- EA = PC + IR(address)

Indexed Addressing Mode (R = IX, where IX: Index

Register)
- EA = IX + IR(address)

Base Register Addressing Mode

(R = BAR, where BAR: Base Address Register)
- EAOrganization
= BAR + IR(address)
CSE 211, Computer
and Architecture

Central Processing Unit

Lecture 25

20

Addressing Mode - Example

Address
PC = 200
R1 = 400
XR = 100

200
201
202

Memory

Load to AC

Address = 500
Next instruction

399
400

450
700

500

800

600

900

702

325

800

300

AC

Addressing
Effective
Mode
Address
Direct address
500
Immediate operand Indirect address
800
Relative address
702
Indexed address
600
Register
Register indirect
400
Autoincrement
400
Autodecrement
399

/* AC (500)
/* AC 500
/* AC ((500))
/* AC (PC+500)
/* AC (RX+500)
/* AC R1
/* AC (R1)
/* AC (R1)+
/* AC -(R)

*/
*/
*/
*/
*/
*/
*/
*/
*/

Content
of AC
800
500
300
325
900
400
700
700
450

CSE 211, Computer Organization and Architecture

Mode

Central Processing Unit

Lecture 26

21

Data Transfer Instructions

Typical Data Transfer Instructions

Name
Load
Store
Move
Exchange
Input
Output
Push
Pop

Mnemonic
LD
ST
MOV
XCH
IN
OUT
PUSH
POP

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 26

22

Data Transfer Instructions

Data Transfer Instructions with Different Addressing M

Assembly
Mode
Convention Register Transfer
Direct address
LD ADR
AC M[ADR]
Indirect address
LD @ADR AC M[M[ADR]]
Relative address LD $ADR AC M[PC + ADR]
Immediate operand
LD #NBR AC NBR
Index addressing LD ADR(X) AC M[ADR + XR]
Register
LD R1
AC R1
Register indirect LD (R1)
AC M[R1]
Autoincrement
LD (R1)+ AC M[R1], R1 R1
+1
Autodecrement
LD -(R1)
R1
R1 - 1, AC M[R1]

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 26

23

Data Maniplulation Instructions

Three Basic Types:

Arithmetic instructions
Logical and bit manipulation
instructions
Shift instructions

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 26

24

Data Manipulation Instructions

Arithmetic Instructions
Name
Increment
Decrement
Add
Subtract
Multiply
Divide
Add with Carry
Subtract with Borrow
Negate(2s Complement)

CSE 211, Computer Organization and Architecture

Mnemonic
INC
DEC
ADD
SUB
MUL
DIV
ADDC
SUBB
NEG

Central Processing Unit

Lecture 26

25

Data Manipulation Instructions

Logical and Bit Manipulation Instructions

Name

Mnemonic

Clear
CLR
Complement
COM
AND
AND
OR
OR
Exclusive-OR
XOR
Clear carry
CLRC
Set carry
SETC
Complement carry
COMC
Enable interrupt
EI
Disable interrupt
DI

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 26

26

Data Manipulation Instructions

Shift Instructions
Name

Mnemonic

Logical shift right

SHR
Logical shift left
SHL
Arithmetic shift right
SHRA
Arithmetic shift left
SHLA
Rotate right
ROR
Rotate left
ROL
Rotate right thru carry
RORC
Rotate left thru carry
ROLC
CSE 211, Computer Organization
and Architecture

Central Processing Unit

Lecture 27

27

Program Control Instruction

PC

+1
In-Line Sequencing (Next instruction is
fetched from the next adjacent location in
the memory)

Address from other source; Current

Instruction, Stack, etc; Branch, Conditional
Subroutine, etc
Program ControlBranch,
Instructions
Name
Branch
Jump
Skip
Call
Return
Compare(by )
Test(by AND)

Mnemonic
BR
JMP
SKP
CALL
RTN
CMP
TST* CMP and TST instructions do not

retain their
results of operations ( and AND,
resp.).
They only set or clear certain

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 27

28

Conditional Branch Instruction

Mnemonic
BZ
BNZ
BC
BNC
BP
BM
BV
BNV

Branch condition

Branch
Branch
Branch
Branch
Branch
Branch
Branch
Branch

if
if
if
if
if
if
if
if

zero
not zero
carry
no carry
plus
minus
overflow
no overflow

Tested condition
Z=1
Z=0
C=1
C=0
S=0
S=1
V=1
V=0

Unsigned compare conditions (A - B)

BHI
Branch if higher
A>B
BHE
Branch if higher or equal A B
BLO
Branch if lower
A<B
BLOE Branch if lower or equal A B
BE
Branch if equal
A=B
BNE
Branch if not equal
AB
Signed compare conditions (A - B)
BGT
Branch if greater than A > B
BGE
Branch if greater or equal A B
BLT
Branch if less than
A<B
BLE
Branch if less or equal A B
BE
Branch if equal
A=B
BNE
Branch if not equal
AB

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 27

29

Subroutine Call and Return

Subroutine Call

Call subroutine
Jump to subroutine
Branch to subroutine
Branch and save return address

Two Most Important Operations are Implied;

* Branch to the beginning of the Subroutine
- Same as the Branch or Conditional Branch
* Save the Return Address to get the address of the location in the Calling Program upon
exit from the Subroutine
Locations for storing Return Address
Fixed Location in the subroutine (Memory)
Fixed Location in memory
In a processor Register
In memory stack
- most efficient way

CALL

RTN

CSE 211, Computer Organization and Architecture

SP SP - 1
M[SP] PC
PC EA
PC M[SP]
SP SP + 1

Central Processing Unit

Lecture 27

30

Flag, Processor Status Word

In Basic Computer, the processor had several (status)

flags 1 bit value that indicated various information
about the processors state E, FGI, FGO, I, IEN, R
In some processors, flags like these are often
combined into a register the processor status
register (PSR); sometimes called a processor status
word (PSW)
Common flags in PSW are

C (Carry): Set to 1 if the carry out of the ALU is 1Status Flag Circuit
S (Sign): The MSB bit of the ALUs output
A
B
8
8
Z (Zero): Set to 1 if the ALUs output is all 0s
c7
V (Overflow): Set to 1 if there is an overflow
c8

8-bit ALU
F7 - F 0

F7

Check for
zero output

F
CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 27

31

Program Interrupt

Types of Interrupts
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device Data transfer request or Data transfer complete
- Timing Device Timeout
- Power Failure
- Operator
Internal interrupts (traps)
Internal Interrupts are caused by the currently running program
- Register, Stack Overflow
- Divide by zero
- OP-code Violation
- Protection Violation
Software Interrupts
Both External and Internal Interrupts are initiated by the computer HW.
Software Interrupts are initiated by the executing an instruction.
- Supervisor Call
1. Switching from a user mode to the supervisor mode
2. Allows to execute a certain class of operations
which are not allowed in the user mode

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 27

32

Interrupt Procedure

Interrupt Procedure and Subroutine

Call

- The interrupt is usually initiated by an internal or an external

signal rather than from the execution of an instruction (except
for the software interrupt)
- The address of the interrupt service program is determined by
the hardware rather than from the address field of an
instruction
- An interrupt procedure usually stores all the information
necessary to define the state of CPU rather than storing only
the PC.
The state of the CPU is determined from:
Content of the PC
Content of all processor registers
Content of status bits
Many ways of saving the CPU state
depending and
on the
CPU architectures
CSE 211, Computer Organization
Architecture

Central Processing Unit

Lecture 28

33

RISC- Historical BackGround

IBM System/360, 1964

The real beginning of modern computer architecture
Distinction between Architecture and Implementation
Architecture: The abstract structure of a computer
seen by an assembly-language programmer
Hardware

-program
Compiler
High-Level
Instruction
Hardware
Language
Set
Architecture

Hardware
Implementation

Continuing growth in semiconductor memory and

microprogramming
A much richer and complicated instruction sets
CISC(Complex Instruction Set Computer)
CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 28

34

CISC

Arguments Advanced at that time

Richer instruction sets would simplify compilers
Richer instruction sets would alleviate the software crisis
move as much functions to the hardware as possible

Richer instruction sets would improve architecture quality

CISC

These computers with many instructions and

addressing modes came to be known as Complex
Instruction Set Computers (CISC)

One goal for CISC machines was to have a machine

language instruction to match each high-level
language statement type

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 28

35

Complex Instruction Set Computers

Another characteristic of CISC computers is that they have

instructions that act directly on memory addresses
For example,
ADD L1, L2, L3
that takes the contents of M[L1] adds it to the contents of M[L2] and
stores the result in location M[L3]

An instruction like this takes three memory access cycles to

execute
That makes for a potentially very long instruction execution
cycle
The problems with CISC computers are
The complexity of the design may slow down the processor,
The complexity of the design may result in costly errors in the processor
design and implementation,
Many of the instructions and addressing modes are used rarely, if ever

CSE 211, Computer Organization and Architecture

Central Processing Unit

Lecture 28

36

Summary : Criticism On CISC

High Performance General Purpose Instructions

- Complex Instruction
Format, Length, Addressing Modes
Complicated instruction cycle control due to the
complex decoding HW and
decoding process

- Multiple memory cycle instructions

Operations on memory data
Multiple memory accesses/instruction

- Microprogrammed control is necessity

Microprogram control storage takes substantial
portion of CPU chip area
Semantic Gap is large between machine instruction
and microinstruction

- General purpose instruction set includes all the

features required by
individually different
applications
CSE
211, Computer Organization and Architecture

Central Processing Unit

Lecture 28

37

RISC Reduced Instruction Set

In the late 70s andComputers
early 80s there was a reaction to

the shortcomings of the CISC style of processors

Reduced Instruction Set Computers (RISC) were
proposed as an alternative
The underlying idea behind RISC processors is to
simplify the instruction set and reduce instruction
execution time
RISC processors often feature:

CSE 211,

Few instructions
Few addressing modes
Only load and store instructions access memory
All other operations are done using on-processor registers
Fixed length instructions
Single cycle execution of instructions
The control unit is hardwired, not microprogrammed
Computer Organization and Architecture

Central Processing Unit

Lecture 28

38

RISC Reduced Instruction Set

Computers

Since all but the load and store instructions use only registers for
operands, only a few addressing modes are needed
By having all instructions the same length, reading them in is
easy and fast
The fetch and decode stages are simple
The instruction and address formats are designed to be easy to
decode
Unlike the variable length CISC instructions, the opcode and
register fields of RISC instructions can be decoded simultaneously
The control logic of a RISC processor is designed to be simple and
fast
The control logic is simple because of the small number of
instructions and the simple addressing modes
The control logic is hardwired, rather than microprogrammed,
because hardwired control is faster

CSE 211, Computer Organization and Architecture