Tutorial 2

RKtiwary

The main simulator window is composed of several views, which

represent different functional parts of the simulated processor.
These are shown in Image1 and are composed of

CPU Instruction memory

Special CPU registers
CPU (general purpose) registers
Program stack
Program creation and running features
Memory in which data is stored
Input, output console

1. CPU instruction
memory view

1. CPU instruction
memory view

Image2 Instruction
memory view

This view contains the program

instructions. The instructions are
displayed as sequences of lowlevel
instruction mnemonics (assembler
level format) and not as binary
code. This is done for clarity and
makes code more readable by
humans.
Each instruction is associated with
two addresses: the physical
address (PAdd) and the logical
address (LAdd). This view also
displays the base address (Base)
against each instruction. The
sequence of instructions belonging

2. Special CPU registers

view

Image 3 Special CPU

registers view

2. Special CPU registers This view shows the set of CPU

registers, which have predefined
view
specialist functions:
PC: Program Counter contains the
address of the next instruction to be
executed.
IR: Instruction Register contains the
instruction currently being executed.
SR: Status Register contains
information pertaining to the result of
the last executed instruction.
SP: Stack Pointer register points to
the value maintained at the top of the
Image 3 Special CPU program stack (see below).
registers view
BR: Base Register contains current

3. CPU registers view

Image 4 CPU

3. CPU registers view

The register set view shows the contents of all
the generalpurpose registers, which are used
to maintain temporary values as the program's
instructions are executed. Registers are very
fast memories that hold temporary values
while the CPU executes instructions.
This architecture supports from 8 to 64
registers. These registers are often used to
hold values of a program's variables as
defined in highlevel languages.
Not all architectures have this many registers.
Some have more (e.g. 128 register) and some
others have less (e.g. 8 registers). In all cases,
these registers serve similar purposes.
This view displays each register's name (Reg),
Image 4 CPU

3. CPU registers view

It can also be used to reset the individual
register values manually which is often useful
for advanced debugging. To manually change
a registers content, first select the register
then enter the new value in the text box, Reg
Value, and click on the CHANGE button in the
Registers tab.
.

Image 4 CPU

4. Program stack
view

Image 5 Program
stack view

4. Program stack
view

The program stack is another area which

maintains temporary values as the
instructions are executed. The stack is a
LIFO (lastinfirstout) data structure. It is
often used for efficient interrupt handling
and subroutine calls. Each program has
its own individual stack.

The CPU instructions PSH (push) and POP

are used to store values on top of stack
Image 5 Program and pop values from top of stack
stack view
respectively.

5. Program list view

Image 6Program
List View

5. Program list view

Use the REMOVE PROGRAM

button to remove the selected
program from the list; use the
REMOVE ALL PROGRAMS button
to remove all the programs from
the list. Note that when a program
is removed, its instructions are also
removed from the Instruction
Memory View too.
Image 6Program
List View

6. Program
creation

Image 7Create
program tab

To create a new program

enter its name in the
Program Name box and
its base address in the
Base Address box then
click on the ADD button.
The new programs name
will appear in the
Program List view (see
Image 6)

Image 8 Add program

instructions tab

Use ADD NEW button to

add a new instruction; use
EDIT button to edit the
selected instruction; use
MOVE DOWN/ MOVE UP
buttons to move the
selected instruction down
or up; use INSERT
ABOVE/INSERT
BELOW buttons to insert
a new instruction above or
below the selected
instruction respectively.

7. Program data
memory view

Image 9
Program data
memory view
The CPU instructions
that access that part
of the memory
containing data can
write or read the
data in addressed
locations. This data
can be seen in the
memory pages
window shown in
Image 9 above. You
can display this
window by clicking

To change the values of any bytes, first select

the line(s) containing the bytes. Then use the
information in the Initialize Data frame to
modify the values of the bytes in the selected
line(s) as Integer, Boolean or String
formats. You need to click the UPDATE
button to make the change

8. IO console view

Appendix Simulator Instruction Subset Inst

Description
Data transfer instructions
MOV
Move data to register; move register to
register
e.g.
MOV #2, R01 moves number 2 into register R01
MOV R01, R03 moves contents of register R01 into
register R03
LDB Load a byte from memory to register
e.g.
LDB 1022, R03 loads a byte from memory address
1022 into R03
LDB @R02, R05 loads a byte from memory the
address of which is in R02
LDW
Load a word (2 bytes) from memory to

STB Store a byte from register to memory

STB R07, 2146 stores a byte from R07 into memory
address 2146
STB R04, @R08 stores a byte from R04 into memory
address of which is in R08
STW Store a word (2 bytes) from register to memory
Same as in STB but a word (i.e. 2 bytes) is loaded stored in
memory
PSH Push data to top of hardware stack (TOS); push register
to TOS
e.g.
PSH #6 pushes number 6 on top of the stack
PSH R03 pushes the contents of register R03 on top of the
stack
POP Pop data from top of hardware stack to register

Arithmetic instructions
ADD Add number to register; add register to register
e.g.
ADD #3, R02 adds number 3 to contents of register R02 and
stores the result in register R02.
ADD R00, R01 adds contents of register R00 to contents of
register R01 and stores the result in register R01.
SUB Subtract number from register; subtract register from
register
MUL Multiply number with register; multiply register with register
DIV Divide number with register; divide register with register

Control transfer instructions

JMP Jump to instruction address unconditionally
e.g.

JLT Jump to instruction address if less than (after last

comparison)
JGT Jump to instruction address if greater than (after last
comparison)
JEQ Jump to instruction address if equal (after last comparison
instruction)
e.g.
JEQ 200 jumps to address location 200 if the previous
comparison instruction result indicates that the two numbers are
equal, i.e. the Z status flag is set (the Z box will be checked in
this case).
JNE Jump to instruction address if not equal (after last
comparison)
MSF Mark Stack Frame instruction is used in conjunction with
the CAL instruction. e.g.

CAL 1456 save the return address in the reserved space

and jump to subroutine in address location 1456
CAL Jump to subroutine address (saves the return
address on program stack)
This instruction is used in conjunction with the MSF
instruction. Youll need an MSF instruction before the CAL
instruction. See the example above
RET Return from subroutine (uses the return address
on stack)
SWI Software interrupt (used to request OS help)
HLT Halt simulation

Comparison instruction
CMP Compare number with register; compare register
with register
e.g.
CMP #5, R02 compare number 5 with the contents of
register R02
CMP R01, R03 compare the contents of registers R01
and R03
Note:
If R01 = R03 then the status flag Z will be set, i.e. the Z
box is checked.
If R03 > R01 then non of the status flags will be set, i.e.
none of the status flag boxes are checked.

Input, output instructions

IN Get input data (if available) from an external IO
device
OUT Output data to an external IO device
e.g.
OUT 16, 0 outputs contents of data in location 16
to the console (the second parameter must always
be a 0)

locate the instruction, which is used to store one byte of data

in a memory location. Use it to store number 65 in address
location 20 (all numbers are in decimal). This is an example
of direct addressing.

1.locate the instruction, which is used to store one byte of

data in a memory location. Use it to store number 65 in
address location 20 (all numbers are in decimal). This is an
example of direct addressing.
STB #65,20
2.Create an instruction to move decimal number 22 to
register R01 and make a note of it below. Execute this
instruction and verify the result in R01.

1.locate the instruction, which is used to store one byte of

data in a memory location. Use it to store number 65 in
address location 20 (all numbers are in decimal). This is an
example of direct addressing.
STB #65,20
2.Create an instruction to move decimal number 22 to
register R01 and make a note of it below. Execute this
instruction and verify the result in R01.
MOV #22,R01

3.Create an instruction to store decimal number 51 in memory

location the address of which is currently stored in register R01.
This is an example of indirect addressing. Note the use of the
@ prefix next to R01 in this case.

3.Create an instruction to store decimal number 51 in memory

location the address of which is currently stored in register R01.
This is an example of indirect addressing. Note the use of the
@ prefix next to R01 in this case.
STB #51,@R01
4. Make a note of what you see in data memory locations 20
and 22

Now, lets create a loop. First, enter the following code. The #
prefix is used to denote a literal value thus distinguishing it
from an address value which does not use it. R01 represents
an arbitrary register; you can use any of the registers from
R00 to R31
MOV #0, R01
ADD #1, R01
CMP #5, R01
JNE 0
HLT
in order to make the code more flexible we can use labels to
represent instruction addresses

Type label name L0 in the box next to the ENTER

LABEL button in the window you use to enter
instructions
Click the ENTER LABEL button
The new code should now look like this (modifications
are in red colour):
MOV #0, R01
L0:
ADD #1, R01
CMP #5, R01
JNE 0

Next, highlight the JNE instruction

Click on the EDIT button
Select L0 in the dropdown list under the Source Operand
section button in the window you use to enter instructions
Click the EDIT button
The new code should now look like this:
MOV #0, R01
L0:
ADD #1, R01
CMP #5, R01
JNE $L0
HLT

Next, highlight the JNE instruction

Click on the EDIT button
Select L0 in the dropdown list under the Source Operand
section button in the window you use to enter instructions
Click the EDIT button
The new code should now look like this:
MOV #0, R01
L0:
ADD #1, R01
CMP #5, R01
JNE $L0
HLT
run this program,
When the program stops make a note of the value in R01 below

create a simple subroutine. Enter the following new

code. You need to create a new label L1 at the start
of the subroutine
Make sure you select the Direct Mem radio button
when entering the first operand value 24 of the
OUT instruction
L1:
OUT 24, 0
RET

Call the subroutine using the instructions MSF (Mark

Stack Frame) followed by CAL
MOV #0, R01
L0:
ADD #1, R01
MSF
CAL $L1
CMP #5, R01
JNE $L0
HLT
L1:
OUT 24,0
RET

Call the subroutine using the instructions MSF (Mark

Stack Frame) followed by CAL
MOV #0, R01
L0:
ADD #1, R01
MSF
CAL $L1
CMP #5, R01
JNE $L0
HLT
L1:
OUT 24,0
RET
Make the out instruction generic

lets get a little bit more ambitious as a challenge. Lets convert the loop
into another subroutine and then call it. So, now we will have two
subroutines where one calls the other. The following code represents this
change
MSF
CAL $L2
HLT
L2:
MOV #0, R01
L0:
ADD #1, R01
MSF
CAL $L1
CMP #5, R01
JNE $L0
RET
L1:
OUT 24,0

Lets make it a bit more

interesting

MSF
PSH #8
CAL $L2
HLT
L2:
POP R02
L0:
ADD #1, R01
MSF
CAL $L1
CMP #5, R01
JNE $L0
L1:
OUT 24,0
RET

Investigating Cache Technology

At the end of this lab you should be able to:
Investigate Directly Mapped cache organization
Explain what cache hit and miss rates are
Understand one drawback of Directly Mapped
cache type
Investigate 2-way Set-Associative cache
mapping
Investigate 4-way Set-Associative cache
mapping
Explain the effect of cache size and mapping

Create a new program, call it CacheTest1 and

enter the following code:
MOV #0, R01
STB R01, @R01
CMP #63, R01
JEQ 31
ADD #1, R01
JMP 6
HLT

The above code writes numbers 0 to 63 in memory locations 0

to 63. Run it and observe the contents of the data in memory.
To see the memory click on the SHOW PROGRAM DATA
MEMORY button.
Click on the SHOW CACHE button to display the data cache
window. Make sure the Stay on top check box is checked. Now,
flush the cache by clicking on the FLUSH button and configure
the cache with the following settings:
Block Size = 4
Cache Type = Direct Mapped
Cache Size = 16
Write Policy = Write-Back

Now insert the following code below the instruction

JMP 6 in the above code:
LDB 0, R00
LDB 1, R00
LDB 2, R00
LDB 3, R00
To execute the above LDB instructions, double-click
on each of the above LDB instructions.

Write down what you observe in the table below:

Addr

Data

Hits

block

Also make a note of the following data displayed in the Cache

Stats frame:
Hits
%Hits
Misses
%Misses
Note: %Hits = 100 - %Misses

Now configure the cache with the following settings:

Block Size = 4
Cache Type = Set Associative
Cache Size = 16
Set Blocks = 2-way
Write Policy = Write-Back
Execute the following set of LDB instructions one after
the other in the order listed below:
LDB 0, R00
LDB 4, R00
LDB 8, R00
LDB 12, R00

Write down your observations below (the Addr field is

filled in for Addr
you):
Set
Block
0000
0004
0008
0012

Next re-configure the cache so that the Set Blocks is set

to 4-way.

Investigating cache size and type on cache

performance
Enter the following program, compile it and load it in CPU
memory:
program CacheTest
var a array(50) byte
i = 49
for n = 0 to 49
p = a(n) + a(i)
i=i-1
next
end

Direct mapping (for cache sizes 16 to 256)

Briefly comment on the results (Tip:

Switch from bar chart to line graph in
the displayed charts and compare the
steepness of the slopes of the graphs
or compare the individual values of
the bars in bar charts):

Investigating Instruction Pipelines

o Demonstrate the difference between pipelined and
sequential processing of the CPU instructions
o Explain pipeline data dependency and data hazard
o Describe a pipeline technique to eliminate data
hazards
o Demonstrate compiler loop unrolling optimizations
benefits for instruction pipelining
o Describe compiler rearranging instructions to
minimize data dependencies
o Show the use of jumppredict table for pipeline
optimisation

Exercise 1 Difference between the sequential and

the pipelined execution of CPU instructions
Enter the following source code, compile it and load in
simulators memory:
program Ex1
for n = 1 to 20
p=p+1
next
end
Now make a note of the following values
CPI (Clocks Per Instruction)
SF (Speedup Factor)