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8086 Architecture

The 8086 microprocessor uses segmented memory architecture to access up to 1MB of memory using four segments - code, data, stack, and extra - each with a base address stored in a segment register, and generates 20-bit physical addresses by combining the segment base with a 16-bit offset. It fetches and buffers up to 6 instruction bytes in an instruction queue to enable pipelined execution for faster processing, and contains status flags like carry, zero, and sign flags updated by the ALU during arithmetic and logical operations.

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160 views12 pages

8086 Architecture

The 8086 microprocessor uses segmented memory architecture to access up to 1MB of memory using four segments - code, data, stack, and extra - each with a base address stored in a segment register, and generates 20-bit physical addresses by combining the segment base with a 16-bit offset. It fetches and buffers up to 6 instruction bytes in an instruction queue to enable pipelined execution for faster processing, and contains status flags like carry, zero, and sign flags updated by the ALU during arithmetic and logical operations.

Uploaded by

Rajaganapathi Rajappan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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8086 Microprocessor Architecture

MEMORY ORGANIZATION
By using 20 address line 8086 can access 1 Mbyte memory
8086 can access four segment at a time
1 Code segment contain program 0000
0
2 Data segment contain data
2000
Code
0
3 Stack segment contain stack data
Seg
2FFF
4 Extra segment contain intermediate
F
400
result
00
Data
Each Segment have 64 Kbyte locations
Seg
Base address is given by respective
4FFFF
segment register
60000
Stack
Seg

Extra
Seg
FFFF
F

6FFFF
80000
8FFFF

Address generation
MP need to generate 20 bit address to access
memory
if code segment = 2000
And Instruction Pointer = 0050
Then 20 bit address is generated as
Code segment Register X 16 (H) = 20000 - Base address
IP
=
0050 - Effective address
(Base add + Eff add)
= 20050 - Physical address
Instruction is fetched from the location 20050

The Instruction Queue:


The BIU can fetches and store up to 6 instruction bytes.
The BIU stores these bytes in first-in-first-out register set
called a queue.
When the EU is ready for executing next instruction it simply
reads the
instruction byte from the queue in the BIU.
This is much faster then fetching single instruction and
executing, then fetching
the next instruction
Fetching the next instruction while the current instruction
executes is called
pipelining

Conditional fag
It reflect the condition of result of the previous operation
Carry flag
It will be set when the carry is generated in the previous operation like
addition
While performing Subtraction it will act as the borrow flag
Parity Flag
It will set when the result contain even no of ones
Auxiliary Carry Flag
It will be set when the carry is generated from the bit D3 to D4 ,while
performing the
arithmetic operation
Zero Flag
It will be set when the result of the previous operation is zero
Sign Flag
It will be copy of the MSB of the result
Over Flow flag
It will be set when the carry is generated from Bit D14 to D15
It is useful when the signed number system is used
Control flag
Control flags are set or reset deliberately to control the operations of the
execution unit.
Trap Flag (TF):
It is used for single step control.

Interrupt Flag (IF):


It is an interrupt enable/disable flag.
If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is
disabled.
It can be set by executing instruction STI and can be cleared by executing
CLI instruction.
Direction Flag (DF):
It is used in string operation.
If it is set, string bytes are accessed from higher memory address to lower
memory address.
When it is reset, the string bytes are accessed from lower memory address
Control
, Arithmetic and Logical Unit
to higherUnit
memory
The
execution unit (EU) of the 8086 tells the BIU from where to fetch
address.
instructions or Data.
It decodes instructions and executes instruction.
A decoder in the EU translates instructions into a series of actions which is
carried by EU
The EU is has a 16-bit ALU which can add, subtract, AND, OR, XOR,
increment, decrement, complement or shift binary numbers.
The EU contains control circuitry which directs internal operations.

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