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9082 CMOS Analog Design Chapter 3

This document discusses CMOS technology components and layout techniques. It covers the CMOS fabrication process flow, device structures like triple well processes, and device parameters for a 180nm technology node. It also summarizes the properties of integrated resistors, capacitors, inductors, and transistors in CMOS technology. Layout techniques like common centroid layouts are described to minimize mismatch between devices. The document discusses optical lithography techniques used in CMOS fabrication. MOSFET layout examples like inverters, differential pairs, and current mirrors are also shown.

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Pankaj jha
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146 views32 pages

9082 CMOS Analog Design Chapter 3

This document discusses CMOS technology components and layout techniques. It covers the CMOS fabrication process flow, device structures like triple well processes, and device parameters for a 180nm technology node. It also summarizes the properties of integrated resistors, capacitors, inductors, and transistors in CMOS technology. Layout techniques like common centroid layouts are described to minimize mismatch between devices. The document discusses optical lithography techniques used in CMOS fabrication. MOSFET layout examples like inverters, differential pairs, and current mirrors are also shown.

Uploaded by

Pankaj jha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 32

CMOS Analog Design Using

All-region MOSFET Modeling


Chapter 3
CMOS technology, components, and
layout techniques

CMOS Analog Design


Using All-Region

Simplified CMOS process flow


Oxide

Photoresist

Nitride

Photoresist

p-type substrate

STI

(a)

STI
STI

STI
p-type substrate

STI

STI

n-well

p+

STI
STI

(f)

Oxide
spacer
+

STI

p+
poly
nwell

p+

STI
STI

(g)

(d)
p+ poly

n+ poly
STI

n+
poly

p-type substrate

p-type substrate

n+

p+
poly
n-well

p-well

Photoresist
Poly
STI

STI

p-type substrate

STI

p-well

pwell

(c)

Photoresist
Poly

Oxide
spacer

STI

n-well

p-type substrate

STI

n+

(b)

STI

p-well

STI

n+
poly

STI

p-well
p-type substrate

p+

p+
n-well

STI
STI

(e)

CMOS Analog Design


Using All-Region

CMOS structure

Transistors in deepsubmicron process


p+

p+

n+

n+

n-well

p-well
deep n-well
p-substrate

Triple-well process
CMOS Analog Design
Using All-Region

180 nm technology node


Parameters of a six-metal-layer 180-nm CMOS technology node
nMOS

pMOS

Supply voltage

1.3 - 1.5V

1.3 - 1.5V

Thin oxide

3 nm

3 nm

Lgate

130 nm

150 nm

VT

0.3 V (130 nm)

-0.24 V (150 nm)

IDsat (1.5V)

0.94 mA/m

0.42 mA/m

Ioff

3 nA/m

3 nA/m

gmsat

860 mS/mm

430 mS/mm

Cj (0V)

0.65 fF/m2

0.95 fF/m2

Silicide ( S, D and poly)

3 - 5 /sq

3 - 5 /sq

CMOS Analog Design


Using All-Region

Integrated resistors
V
FL
L
R

I ( hW )qnv ( hW )qn

L
R
W
1
SH

1
L
RSH

hq n W

h
q nh

W
h

In the general case


h
1
SH
0

q ndx
CMOS Analog Design
Using All-Region

Resistivity of some metals


Metal (bulk)

Resistivity at 20 oC

TCR

Aluminum

2.810-6 -cm

3800 ppm/oC

Copper

1.710-6 -cm

4000 ppm/oC

Gold

2.410-6 -cm

3700 ppm/oC

Sheet resistance of a copper layer of 1000 nm depth

RSH

1.7 106 cm

17 m/sq
4
h
10 cm

CMOS Analog Design


Using All-Region

Polysilicon resistors

CMOS Analog Design Using All-Region MOSFET


Modeling

CMOS Analog Design


Using All-Region

77

Summary of resistors in CMOS technology


Resistor type

Sheet resistance
(/sq)

Temperature
coefficient
(ppm/oC)

Voltage
coefficient
(ppm/V)

n+ Polysilicon

100

-800

50

p+ Polysilicon

200

200

50

n+/ p+ Polysilicon
(silicided)

n+ Diffusion

50

1500

500

p+ Diffusion

100

1500

500

n-Well

1000

2500

10000

CMOS Analog Design


Using All-Region

The MOS transistor as a resistor


dI
1
D
R VDS 0 dVD

VDS 0

dI D
dVS

g ms
VDS 0

2I S
t

1 if 1

Example: Verify that, in strong inversion, the equivalent resistance


between source and drain of an MOS transistor at VDS=0 is given
by

1
W VG VT 0

g ms ( d ) Cox n
VQ
R VDS 0
L
n

VQ is the dc potential at the source.

CMOS Analog Design


Using All-Region

Metal-insulator-metal capacitors
C=C1+C2+C3

Top view

Metal 4
C1
Metal 3
C2
Metal 2
C3
Metal 1
Cparasitic
Cross section
Substrate

(a)

(b)

(a) vertical parallel plate structure, (b) lateral flux capacitor.


CMOS Analog Design
Using All-Region

10

Metal-oxide semiconductor capacitors



Cgb

(a) Poly-semiconductor

C ox2
VCC
3q s N A

1
1
1

Cc Cox

(b) poly-poly capacitors


1 dA 1 dtox
dCc 1 d ox
Cox
1 d ox

ox dT
Cc2 dT ox dT
A dT tox dT

TCC

VCC is typically around 100 ppm/V


TCC is of the order of 20 ppm/oC.
CMOS Analog Design
Using All-Region

11

MOSFET gate capacitors - 1

Gate capacitors in a p-well CMOS technology

CMOS Analog Design


Using All-Region

12

MOSFET gate capacitors - 2

experiment

theory

CMOS Analog Design


Using All-Region

13

MOSFET gate capacitors - 3


In strong inversion

C gs Cgd

1
Cox
2

C gb 0
In accumulation

Cgs Cgd 0
Intrinsic capacitances of the
MOS transistor for VDS=0

Cgb Cox

CMOS Analog Design


Using All-Region

14

MOSFET gate capacitors - 4


In accumulation

2t
Cox
1
C gb
2t VFB VG s

VCC

2t

C
1

ox

V
t
FB
G

2t

VFB VG

In inversion, a similar expression holds

VCC

2t

VG VT

CMOS Analog Design


Using All-Region

15

Summary of capacitors in CMOS


Capacitor type

Capacitance per
unit area
( aF/m2)

Temperature
coefficient
(ppm/C)

Voltage
coefficient
(ppm/V)

MOM

150

20

10

MOM (combined
lateral and vertical
structure)

200

20

10

MOS gate (biased)

5000

200

10000

MOS (heavily doped


Si option)

1000

20

10

MIM (thin oxide


option)

1000

20

10

Poly-poly

1000

20

10

CMOS Analog Design Using All-Region MOSFET


Modeling

CMOS Analog Design


Using All-Region

16
16

Inductors
Example: Inductance of a 5turn spiral inductor with an
average radius of 50 m .
L n 2 0 r
52 4
10
7 50 106

1.6 nH

Planar spiral inductor


CMOS Analog Design
Using All-Region

17

Bipolar transistors (BJTs) in CMOS

Flow of carriers in the CMOS-compatible bipolar junction transistor

CMOS Analog Design


Using All-Region

18

BJTs in triple-well CMOS

CMOS Analog Design


Using All-Region

19

Latchup

Parasitic bipolar transistors in CMOS technology which may lead


to latchup. (a) Cross section of the CMOS structure; (b)
Equivalent circuit of the parasitic bipolar transistors and resistors

CMOS Analog Design


Using All-Region

20

Optical lithography - 1
Ultraviolet light

Mask

Photoresist
Wafer

CMOS Analog Design


Using All-Region

21

Optical lithography - 2
Wavelength used for optical lithography
Source

Wavelength
(nm)

Intended
resolution (nm)

Year of
introduction

G-line *

436

1000

I-line *

365

500

1984

KrF laser

248

250

1989

ArF laser

193

100

2001

F2 laser

157

65

**

*Filtered spectral components of high-pressure Hg or Hg-rare gas discharge lamps.


** The technology was abandoned.

CMOS Analog Design


Using All-Region

22

Optical lithography - 3

Optical proximity correction (OPC) counteracts lithography distortions

CMOS Analog Design


Using All-Region

23

MOSFET layout - 1

Mask layout and cross section of a CMOS inverter. N-well and P-well
contacts not shown. Dashed lines represent metal connections
CMOS Analog Design
Using All-Region

24

MOSFET layout - 2
Source/drain
implant

Shaded region

Asymmetr
y

Diagonal shift in the source drain regions of


a transistor due to a tilted implant

CMOS Analog Design


Using All-Region

25

MOSFET layout - 3
Rules for minimizing systematic
mismatch of integrated devices
No
1

Rule
Same structure

Same shape, same size

Same orientation

Same surroundings

Minimum distance

Common-centroid geometries

Same temperature
CMOS Analog Design
Using All-Region

26

MOSFET layout - 4
Unconnected
dummy

Conn.
dummy

Unconnected
dummy

Conn.
dummy

Matching improvement by the addition of dummy devices for the


layout of two resistors with a resistance ratio of 2/1: (a)
unconnected dummy resistors (b) connected dummy resistors
CMOS Analog Design Using All-Region MOSFET
Modeling

CMOS Analog Design


Using All-Region

27
27

MOSFET layout - 5
B

(a)

A
Cox

B
Cox+Cox

(b)

Cox+2Cox

A
Cox+3Cox

Mock layouts of some possible common-centroid geometries for


improved matching. Transistors with the same label are connected
in parallel.
CMOS Analog Design
Using All-Region

28

MOSFET layout - 6
D

C
A

C
C

A differential pair with a folded layout


CMOS Analog Design
Using All-Region

29

MOSFET layout - 7
D
A

E
B

F
G

E
C

C
G

A third device is added to the differential pair


without degrading the symmetry of the layout
CMOS Analog Design
Using All-Region

30

MOSFET layout - 8
E

B
C
C
Common-centroid layout of a differential pair.
CMOS Analog Design Using All-Region MOSFET
Modeling

CMOS Analog Design


Using All-Region

31
31

MOSFET layout - 9
Iin
Iout
Iout

Iin

(a)

(b)

Current mirror with an attenuation factor of 16: (a) Schematic; (b)


Mock layout.
CMOS Analog Design
Using All-Region

32

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