Lecture 12

Finite State Machine Design

Prith Banerjee
ECE C03
Advanced Digital Design
Spring 1998
ECE C03 Lecture 12

Outline
Review of sequential machine design
Moore/Mealy Machines
FSM Word Problems
Finite string recognizer
Traffic light controller

READING: Katz 8.1, 8.2, 8.4, 8.5, Dewey 9.1, 9.2

ECE C03 Lecture 12

Concept of the State Machine

Computer Hardware = Datapath + Control

Registers
Combinational Functional
Units (e.g., ALU)
Busses

Qualifiers

Control

Control

FSM generating sequences

of control signals
Instructs datapath what to
do next

"Puppeteer who pulls the

strings"

State
Control
Signal
Outputs

Qualifiers
and
Inputs

"Puppet"

Datapath

ECE C03 Lecture 12

Example: Odd Parity Checker

Assert output whenever input bit stream has odd # of 1's

Reset
0

Even
[0]
1

1
Odd
[1]

State
Diagram

Present State
Even
Even
Odd
Odd

Input
0
1
0
1

Next State
Even
Odd
Odd
Even

Output
0
0
1
1

Symbolic State Transition Table

Present State
0
0
1
1

Input
0
1
0
1

Next State Output

0
0
1
0
1
1
0
1

Encoded State Transition Table

ECE C03 Lecture 12

Odd Parity Checker Design

Next State/Output Functions
NS = PS xor PI; OUT = PS

Input

NS
Input

CLK
R

CLK

PS/Output

\Reset
T FF Implementation

D FF Implementation
1

Output

Q
R

\Reset

Input

Clk

Output

Timing Behavior:
Input
10011
ECE C03
Lecture
120 1 0 1 1 1 0

Timing of State Machines

When are inputs sampled, next state computed, outputs asserted?
State Time: Time between clocking events
Clocking event causes state/outputs to transition, based on inputs
For set-up/hold time considerations:
Inputs should be stable before clocking event
After propagation delay, Next State entered, Outputs are stable
NOTE: Asynchronous signals take effect immediately
Synchronous signals take effect at the next clocking event
E.g., tri-state enable: effective immediately
sync. counter clear: effective at next clock event

ECE C03 Lecture 12

Timing of State Machine

Example: Positive Edge Triggered Synchronous System
State Time

Clock

On rising edge, inputs sampled

outputs, next state computed
After propagation delay, outputs and
next state are stable

Inputs

Immediate Outputs:
affect datapath immediately
could cause inputs from datapath to change

Outputs

Delayed Outputs:
take effect on next clock edge
propagation delays must exceed hold times

ECE C03 Lecture 12

Communicating State Machines

One machine's output is another machine's input
X
FSM 2

FSM 1

CLK

FSM 1
Y=0

Y=0
A
[1]

X=0

X=0
C
[0]

X
FSM 2

X=1
Y=0,1

X=1

Y=1

B
[0]

X=0

D
[1]

Machines advance in lock step

Initial inputs/outputs: X = 0, Y = 0

ECE C03 Lecture 12

Basic Design Approach

1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state mininimization
4. Perform state assignment
5. Choose FF types to implement FSM state register
6. Implement the FSM
1, 2 covered now; 3, 4, 5 covered later;
4, 5 generalized from the counter design procedure

ECE C03 Lecture 12

Example: Vending Machine FSM

General Machine Concept:
deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
Step 1. Understand the problem:
Draw a picture!
Block Diagram

N
Coin
Sensor

D
Reset

Vending
Machine
FSM

Open

Gum
Release
Mechanism

Clk

ECE C03 Lecture 12

10

Vending Machine Example

Step 2. Map into more suitable abstract representation
Reset

Tabulate typical input sequences:

three nickels
nickel, dime
dime, nickel
two dimes
two nickels, dime
Draw state diagram:

N
S1

Inputs: N, D, reset
Output: open

D
S2

S4

S5

S6

[open]

[open]

[open]

S3

S0

S7

S8

[open]

[open]

ECE C03 Lecture 12

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Vending Machine Example

Step 3: State Minimization
Present
State

Reset
0

0
N
5
D

N
10
D

10

N, D
15
[open]

15

reuse states
whenever
possible

Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
X

0
1
0
1
0
1
0
1
0
1
0
1
X

Next
State

Output
Open

0
5
10
X
5
10
15
X
10
15
15
X
15

0
0
0
X
0
0
0
X
0
0
0
X
1

Symbolic State Table

ECE C03 Lecture 12

12

Vending Machine Example

Step 4: State Encoding
Present State Inputs
Q1 Q0
D N
0

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Next State
D1 D0

Output
Open

0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X

0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X

ECE C03 Lecture 12

13

Vending Machine Example

Step 5. Choose FFs for implementation
Q1

Q1 Q0
DN
0

Q1 Q0
DN

N
D

Q0
K-map for D1
Q1
D
Q0
N
N
\ Q0
Q0
\N
Q1
N
Q1
D

D1

D FF easiest to use
Q1
1

N
D

Q0
K-map for D0
D

CLK

Q1

\ Q1

Q1

Q1 Q0
DN
0

Q0
K-map for Open

D1 = Q1 + D + Q0 N

\reset
OPEN

D0

CLK
\reset

Q0

\ Q0

D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
8 Gates

ECE C03 Lecture 12

14

Alternative State Machine

Representations

Why State Diagrams Are Not Enough

Not flexible enough for describing very complex finite state machines
Not suitable for gradual refinement of finite state machine
Do not obviously describe an algorithm: that is, well specified
sequence of actions based on input data
algorithm = sequencing + data manipulation
separation of control and data

Gradual shift towards program-like representations:

Algorithmic State Machine (ASM) Notation
Hardware Description Languages (e.g., VHDL)

ECE C03 Lecture 12

15

Alternative State Machine

Representations
Algorithmic State Machine (ASM) Notation
Three Primitive Elements:
State Box
State
Entry Path

Decision Box
Output Box

State Code

State Machine in one state

block per state time
Single Entry Point
Unambiguous Exit Path
for each combination
of inputs
Outputs asserted high (.H)
or low (.L); Immediate (I)
or delayed til next clock

State
Name
State
Output List
T

***
State Box

Condition

Condition
Box
Conditional
Output List

ECE C03 Lecture 12

ASM
Block

Output
Box

Exits to
other ASM Blocks

16

ASM Notation
Condition Boxes:
Ordering has no effect on final outcome
Equivalent ASM charts:
A exits to B on (I0 I1) else exit to C
A

010

I0
T

010

I1
T

F
I1

F
F

I0

T
B

ECE C03 Lecture 12

17

ASM Example: Parity Checker

Input X, Output Z
Even

Nothing in output list implies Z not asserted

Z asserted in State Odd
F

Symbolic State Table:

T
Odd

Present Next
Input State
State Output
F

Even
Even
T

Even
Odd
F
A
Odd
Odd
T
A
Odd
Even

1
H.Z

Encoded State Table:

Trace
Tracepaths
pathsto
toderive
derive
state
transition
state transitiontables
tables

Present Next
Input State
State Output
0
0
0
0
1
0
0
1
0
1
1
1
1
1
1
0

ECE C03 Lecture 12

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ASM Chart: Vending Machine

0

00

10

10

F
F

F
F

15

01

11

H.Open
T

Reset

F
F

T
T

ECE C03 Lecture 12

19

Moore and Mealy Machine Design

Procedure
Moore Machine
Xi
Inputs

Zk
Outputs

Combinational
Logic for
Outputs and
Next State

State Register

Clock

Outputs are function

solely of the current
state
Outputs change
synchronously with
state changes

State
Feedback

State
Register
Xi
Inputs

Mealy Machine

Comb.
Logic for
Outputs

Combinational
Logic for
Next State
(Flip-flop
Inputs)

Zk
Outputs
Clock

state
feedback

ECE C03 Lecture 12

Outputs depend on
state AND inputs
Input change causes
an immediate output
change
Asynchronous signals

20

Equivalence of Moore and Mealy

Machines
Moore
Machine

(N D + Reset)/0

Reset/0

N D + Reset
Reset

0
Reset/0

[0]

Reset

N/0

N
5

5
N D/0

D/0

ND

[0]

N/0

10

10
D

D/1

Mealy
Machine

N D/0
N+D/1

[0]
N+D

ND

15

15

[1]

Reset/1

Outputs are associated

with State

Reset

Outputs are associated

with Transitions

ECE C03 Lecture 12

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States vs Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
0/0

0
[0]

Same I/O behavior

Different # of states

1/0

0/0

1
1/1

[0]
1
2
[1]

S0

00

S0

IN
S1

IN
01

IN
S2

S1

Equivalent
ASM Charts

IN
10

H.OUT
IN

H.OUT

ECE C03 Lecture 12

22

Analyze Behavior of Moore Machines

Reverse engineer the following:
X
X
\B

J
Q
C
KR Q
FFa

A
\A

Input X
Output Z
State A, B = Z

\Reset

Clk
X
X
\A

J
Q
C
KR Q
FFb

Z
\B

\Reset

Two Techniques for Reverse Engineering:

Ad Hoc: Try input combinations to derive transition table
Formal: Derive transition by analyzing the circuit

ECE C03 Lecture 12

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Ad Hoc Reverse Engineering

Behavior in response to input sequence 1 0 1 0 1 0:
100
X
Clk
A
Z
\Reset
Reset
X =1
X =0
X=1
X=0
X=1
X=0
X=0
AB = 00 AB = 00 AB = 11 AB = 11 AB = 10 AB = 10 AB = 01 AB = 00
A B
0 0

Partially Derived
State Transition
Table

0 1
1 0
1 1

X
0
1
0
1
0
1
0
1

ECE C03 Lecture 12

A+
?
1
0
?
1
0
1
1

B+
?
1
0
?
0
1
1
0

Z
0
0
1
1
0
0
1
1

24

Formal Reverse Engineering

Derive transition table from next state and output combinational
functions presented to the flipflops!
Ja = X
Jb = X

Z=B

Ka = X B
Kb = X xor A

FF excitation equations for J-K flipflop:

A+ = Ja A + Ka A = X A + (X + B) A
B+ = Jb B + Kb B = X B + (X A + X A) B
Next State K-Maps:

A+

State 00, Input 0 -> State 00

State 01, Input 1 -> State 01

B+

ECE C03 Lecture 12

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Complete ASM Chart of Moore Machine

00

S0

11

S3
H.Z

X
1

S1

01

S2

10

H.Z
0

Note: All Outputs Associated With State Boxes

No Separate Output Boxes Intrinsic in Moore Machines

ECE C03 Lecture 12

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Behavior of Mealy Machines

Clk

DA

D
C

Q
R Q

\A
X

\A

\X

J
Q
C
KR Q

\Reset

A
X

B
\B

\Reset

DA

\X
B

Z
\X

X
A

Input X, Output Z, State A, B

State register consists of D FF and J-K FF

ECE C03 Lecture 12

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Ad Hoc Reverse Engineering

Signal Trace of Input Sequence 101011:

100

Note glitches
in Z!

Clk
A

Outputs valid at
following falling
clock edge

B
Z
\Reset
Reset
AB=00
Z =0

X =1
AB=00
Z =0

X =0
AB=00
Z =0

X =1
AB=01
Z =0

X =0
AB=11
Z=1

X
0
1
Partially completed
0 1
0
state transition table
1
based on the signal
1 0
0
trace
1
1 1
0
1
ECE C03 Lecture

X =1
AB=10
Z =1

A B
0 0

12

A+
0
0
?
1
?
0
1
?

X =1
AB=01
Z =0

B+
1
0
?
1
?
1
0
?

Z
0
0
?
0
?
1
1
?

28

Formal Reverse Engineering

A+ = B (A + X) = A B + B X
B+ = Jb B + Kb B = (A xor X) B + X B
= A B X + A B X + B X
Z

= A X + B X

A+

Missing Transitions and Outputs:

State 01, Input 0 -> State 01, Output 1
State 10, Input 0 -> State 00, Output 0
State 11, Input 1 -> State 11, Output 1

B+

ECE C03 Lecture 12

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ASM Chart of Mealy Machine

S0 = 00, S1 = 01, S2 = 10, S3 = 11

S0

H. Z

00

0
X
0

S1

10

S2

H. Z

X
1

S3

01

11
H.Z

X
0

NOTE: Some Outputs in Output Boxes as well as State Boxes

This is intrinsic in Mealy Machine implementation

ECE C03 Lecture 12

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Synchronous Mealy Machines

Clock
Xi
Inputs

Zk
Outputs

Combinational
Logic for
Outputs and
Next State
State Register

Clock

state
feedback

latched state AND outputs

avoids glitchy outputs!

ECE C03 Lecture 12

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Finite State Machine Word Problems

Mapping English Language Description to Formal Specifications

Case Studies:
Finite String Pattern Recognizer
Traffic Light Controller

We will use state diagrams and ASM Charts

ECE C03 Lecture 12

32

Finite String Pattern Recognizer

A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence 010
has been observed, as long as the sequence 100 has never been
seen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010
Z: 00010101000
X: 11011010010
Z: 00000001000

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Finite String Recognizer

Step 2. Draw State Diagrams/ASM Charts for the strings that must be
recognized. I.e., 010 and 100.
S0
[0]

Outputs 1

Reset

S1
[0]

S4
[0]

S2
[0]

S5
[0]

S3
[1]

S6
[0]

Moore State Diagram

Reset signal places
FSM in S0

Loops in State

ECE C03 Lecture 12

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Finite String Recognizer

Exit conditions from state S3: have recognized 010
if next input is 0 then have 0100!
if next input is 1 then have 0101 = 01 (state S2)
S0
[0]

Reset

S1
[0]

S4
[0]

S2
[0]

S5
[0]

S3
[1]

S6
[0]

ECE C03 Lecture 12

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Finite String Recognizer

Exit conditions from S1: recognizes strings of form 0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form 1 (no 0 seen)
loop back to S4 if input is 1
S0
[0]

Reset

S1
[0]

S4
[0]

S2
[0]

S5
[0]

S3
[1]

S6
[0]

ECE C03 Lecture 12

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Finite String Recognizer

S2, S5 with incomplete transitions
S2 = 01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!
S5 = 10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
S0
[0]

Reset

S1
[0]

S4
[0]

S2
[0]

S5
[0]

S3
[1]

S6
[0]

ECE C03 Lecture 12

Final State Diagram

37

Review of Design Process

Write down sample inputs and outputs to understand specification
Write down sequences of states and transitions for the sequences
to be recognized
Add missing transitions; reuse states as much as possible
Verify I/O behavior of your state diagram to insure it functions
like the specification

ECE C03 Lecture 12

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Traffic Light Controller

A busy highway is intersected by a little used farmroad. Detectors
C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.

ECE C03 Lecture 12

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Traffic Light Controller

Picture of Highway/Farmroad Intersection:
Farmroad
C

HL

FL

Highway

Highway
HL

FL
C
Farmroad

ECE C03 Lecture 12

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Traffic Light Controller

Tabulation of Inputs and Outputs:
Input Signal
reset
C
TS
TL

Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired

Output Signal
HG, HY, HR
FG, FY, FR
ST

Description
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval

Tabulation of Unique States: Some light configuration imply others

State
S0
S1
S2
S3

Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)

ECE C03 Lecture 12

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Traffic Light Controller

Refinement of ASM Chart:
Start with basic sequencing and outputs:

S0

S3

H.HG
H.FR

H.HR
H.FY

S1
H.HY
H.FR

S2
H.HR
H.FG

ECE C03 Lecture 12

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Traffic Light Controller

Determine Exit Conditions for S0:
Car waiting and Long Time Interval Expired- C TL
S0

S0

H.HG
H.FR
0

H.HG
H.FR
0

TL

TL C

1
0

1
H.ST

1
H.ST

S1
H.HY
H.FR

S1
H.HY
H.FR

Equivalent ASM Chart Fragments

ECE C03 Lecture 12

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Traffic Light Controller

S1 to S2 Transition:
Set ST on exit from S0
Stay in S1 until TS asserted
Similar situation for S3 to S4 transition

S1
H.HY
H.FR
0

TS

H.ST

S2
H.HR
H.FG

ECE C03 Lecture 12

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Traffic Light Controller

S2 Exit Condition: no car waiting OR long time interval expired

S0
H.HG
H.FR
0

H.ST
1

TL C

S3
H.HR
H.FY

TS

1
H.ST

S1
H.HY
H.FR
0

TS

H.ST

H.ST

S2
H.HR
H.FG

TL + C
1

Complete ASM
Chart
forLecture
Traffic Light
ECE
C03
12 Controller

45

Traffic Light Controller

Compare with state diagram:
TL + C
Reset
S0
TLC/ST

TS/ST

S1: HY

TS
S1

S2: FG

S3
TS

TS/ST
S2

S0: HG

S3: FY

TL + C/ST
TL C

Advantages of State Charts:

Concentrates on paths and conditions for exiting a state
Exit conditions built up incrementally, later combined into
single Boolean condition for exit
Easier to understand
theLecture
design as
ECE C03
12an algorithm

46

Summary
Review of sequential machine design
Moore/Mealy Machines
FSM Word Problems
Finite string recognizer
Traffic light controller

NEXT LECTURE: Finite State Machine

Optimization
READING: Katz 9.1, 2.2.1, 9.2.2, Dewey 9.3

ECE C03 Lecture 12

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