Sigma Delta

ES585a - Computer Based Power System Protection
Course by Dr.T.S.Sidhu - Fall 2005

Class discussion presentation by
Vijayasarathi Muthukrishnan
25th October 2005
Department of Electrical & Computer Engineering
Types of A/D Converters
Recap of terminology
Over-sampling
Noise shaping
Introducing Sigma-Delta Converters (ADC)
Functional description & Simulations
Comparison with other converters
Applications & Relevance to Protection
industry
Sampling
Sampling rate & Nyquist interval
Quantization
Quantizer resolution
Quantization error
Quantization noise
Example:
Fmax = 60 Hz
Minimum sampling rate
Fs = 120 Hz (Nyquist
rate)
Over sampling rate
Fs = 7680 Hz (Say
64*fs)
60 Hz signal sampled at 600 Hz ( 5 times Nyquist rate )
Magnitude
0.5
0
-0.5
-1
0.002
0.004
0.006
0.008
0.01
Time
0.012
0.014
0.016
0.018
0.02
60 Hz signal sampled at 7680 Hz ( 64 times Nyquist rate)
1
0.5
Magnitude
Sampling at a higher rate

which is a larger multiple
of normal Nyquist rate.
0
-0.5
-1
0.002
0.004
0.006
0.008
0.01
Time
0.012
0.014
0.016
0.018
0.02
Anti-aliasing filter requirements are greatly

reduced.
Reduces the quantization noise within the
frequency range of interest.
Frequency spectrum for Normal sampling condition
Magnitude
With Sharp cut-off Anti-aliasing filter
Fmax
Frequency
Fs
Frequency spectrum for Over-sampling condition
Magnitude
With Wide roll-off Anti-aliasing filter
Fmax
Fs
Frequency
Quantization noise - Nyquist rate sampling
Quantization noise Over sampling
Quantization noise after filtering
10
The efficiency of Noise

reduction is increased in
the frequency range of
interest if Noise shaping
filters are used in an over
sampled system.
These filters reduce the
quantization noise by
pushing them out of the
frequency range of
interest.
11
High resolution low cost ADC.

Made possible by the chips that integrate both analog
and digital circuitry.
Over sampling and Noise shaping concepts are applied.
Circuit uses Comparators (Delta) and Integrators (Sigma)
and so the name : DELTA-SIGMA or SIGMA-DELTA
12
1-Bit stream
(1 or 0)
+1 or -1 volt
1 Bit DAC
13
X1
1-Bit stream
(1 or 0)
+1 or -1 volt
1 Bit DAC
X1
X2 = X1-X5
X3 = X2 + X3(n-1)
IF X3 > 0
X4 = 1
X5 = +1
IF X3 < 0
X4 = 0
X5 = -1
X2
X3
X4
X5
0.5
-0.5
-0.5
-1
0.6
1.6
1.1
0.7
-0.3
0.8
0.8
-0.2
0.6
0.9
-0.1
0.5
0.5
0.9
-0.1
0.4
0.8
-0.2
0.2
0.7
-0.3
-0.1
-1
0.6
1.6
`.5
0.5
-0.5
0.3
-0.7
0.3
-1
-0.7
-1
-0.2
0.8
0.1
-0.4
-1.4
-1.3
-1
-0.6
0.4
-0.9
-1
-0.8
0.2
-0.7
-1
-1
-0.7
-1
-0.8
0.2
-0.5
-1
-0.6
1.6
1.1
-0.4
-1.4
-0.3
-1
-0.2
0.8
0.5
-1
-0.5
-1
14
X1
X2 = X1-X5
X3 = X2 + X3(n-1)
IF X3 > 0
IF X3 < 0
X4 = 1
X4 = 0
X5 = +1
X5 = -1
15
X1
Density of ones is
more when the
input is more
positive.
Density of zeros
is more when input
is more negative.
X2
X3
X4
X5
0.5
-0.5
-0.5
-1
0.6
1.6
1.1
0.7
-0.3
0.8
0.8
-0.2
0.6
0.9
-0.1
0.5
0.5
0.9
-0.1
0.4
0.8
-0.2
0.2
0.7
-0.3
-0.1
-1
0.6
1.6
`.5
0.5
-0.5
0.3
-0.7
0.3
-1
-0.7
-1
-0.2
0.8
0.1
-0.4
-1.4
-1.3
-1
-0.6
0.4
-0.9
-1
-0.8
0.2
-0.7
-1
-1
-0.7
-1
-0.8
0.2
-0.5
-1
-0.6
1.6
1.1
-0.4
-1.4
-0.3
-1
-0.2
0.8
0.5
-1
-0.5
-1
16
Fs = 32*Fs
1
Input
0.5
0
-0.5
-1
20
40
60
80
100
120
20
40
60
80
100
120
20
40
60
80
100
120
DAC
0.5
0
-0.5
-1
Sigma Delta Output
1
0.8
0.6
0.4
0.2
0
17
Fs = 64*Fs
1
Input
0.5
0
-0.5
-1
50
100
150
200
250
300
350
400
450
500
50
100
150
200
250
300
350
400
450
500
50
100
150
200
250
300
350
400
450
500
DAC
0.5
0
-0.5
-1
Sigma Delta Output
1
0.8
0.6
0.4
0.2
0
18
The input is an analog signal over sampled at Fs.

Use of 1-bit ADC simplifies the structure.
The output of this ADC is a stream of 1 bit data i.e. 1s & 0s generated at very
high clock rate which is nothing but Fs
The feedback loop ensures that the average output level is equal to the input
signal level.
A decimation filter is used to average and get the digital output from the
stream of one bits.
The resolution at converter output i.e. no of bits is also increased after
decimation.
19
Everything is in Digital domain : Low pass filter + Down

sampler.
Acts as a low pass filter and removes the high frequency
quantization noise and other remains of high frequency
components.
Averages the stream of one bits
Finally reduction to original sampling rate Fs from over
sampled rate Fs
Higher bit resolution is also achieved
20
16:1 Decimation
16 - one bit stream
Analog input
1100000110000011
SIGMA DELTA
BLOCK
Over sampled
at 16 times
Avg.= (6/16 )= 0.375
DECIMATION
FILTER
0110
One 4 - bit representation
21
Decimation from fs' = 30720 Hz to fs = 1920 Hz (16:1)
Decim ated output Sigma D elta Output
Input
-1
100
200
300
400
500
600
700
800
900
1000
100
200
300
400
500
600
700
800
900
1000
0.5
0
1
-1
10
20
30
40
50
60
22
Decimation from fs'=15360 Hz to fs= 960 Hz (16:1)
Input
1
0
Decimated output Sigma Delta Output
-1
50
100
150
200
250
300
350
400
450
500
50
100
150
200
250
300
350
400
450
500
0.5
0
1
0
-1
10
15
20
25
30
23
Decimation from fs'=7680 Hz to fs=480 Hz (16:1)
Decimated output Sigma Delta Output
Input
1
0
-1
50
100
150
200
250
50
100
150
200
250
0.5
0
1
0
-1
10
15
24
Z-domain analysis of this

converter reveals that
the noise is High-pass
filtered [Hn(Z) = (Z-1)/Z]
i.e. noise is pushed out
of our range of interest.
Low pass filtering in
Decimation filter
removes all out of band
noise leading to very
minimum noise within
our range of interest.
25
Merits
High resolution at Low cost
Very efficient noise handling
Less stringent Anti-aliasing filter requirements
Demerits
Several clock cycles settling time or latency due to delays in
digital filtering stage
Longer conversion time, typically 100000 samples/s for 16-bit
resolution and 1000 samples/s for 24-bit resolution
Limited to low frequency applications as over sampling
becomes tough for high frequency applications
26
27
Process applications
Temperature measurements
Digital Audio CD system applications
Latency is the major issue which keeps the
protection industry away from sigma delta ADC
28
An over view of sigma delta converters IEEE Signal Processing

Magazine, 1996
Motorola Sigma Delta converter Application note
MAXIM Semiconductors Sigma delta converter Application note
Intersil corporation Sigma Delta converter Application note
Introduction to Signal Processing book by Sophocles J. Orfanidis
Understanding DSP book by Richard G.Lyons
29
30

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ES585a - Computer Based Power System Protection

Course by Dr.T.S.Sidhu - Fall 2005

Department of Electrical & Computer Engineering

Types of A/D Converters

Department of Electrical & Computer Engineering

Department of Electrical & Computer Engineering

60 Hz signal sampled at 600 Hz ( 5 times Nyquist rate )

60 Hz signal sampled at 7680 Hz ( 64 times Nyquist rate)

Sampling at a higher rate

Department of Electrical & Computer Engineering

Anti-aliasing filter requirements are greatly

Department of Electrical & Computer Engineering

Frequency spectrum for Normal sampling condition

With Sharp cut-off Anti-aliasing filter

Frequency spectrum for Over-sampling condition

With Wide roll-off Anti-aliasing filter

Department of Electrical & Computer Engineering

Quantization noise - Nyquist rate sampling

Department of Electrical & Computer Engineering

Quantization noise Over sampling

Department of Electrical & Computer Engineering

Quantization noise after filtering

Department of Electrical & Computer Engineering

The efficiency of Noise

Department of Electrical & Computer Engineering

High resolution low cost ADC.

Department of Electrical & Computer Engineering

Department of Electrical & Computer Engineering

Department of Electrical & Computer Engineering

Department of Electrical & Computer Engineering

Department of Electrical & Computer Engineering

Sigma Delta Output

Department of Electrical & Computer Engineering

Sigma Delta Output

Department of Electrical & Computer Engineering

The input is an analog signal over sampled at Fs.

Department of Electrical & Computer Engineering

Everything is in Digital domain : Low pass filter + Down

Avg.= (6/16 )= 0.375

Department of Electrical & Computer Engineering

Decimation from fs' = 30720 Hz to fs = 1920 Hz (16:1)

Decim ated output Sigma D elta Output

Department of Electrical & Computer Engineering

Decimation from fs'=15360 Hz to fs= 960 Hz (16:1)

Decimated output Sigma Delta Output

Department of Electrical & Computer Engineering

Decimation from fs'=7680 Hz to fs=480 Hz (16:1)

Decimated output Sigma Delta Output

Department of Electrical & Computer Engineering

Z-domain analysis of this

Department of Electrical & Computer Engineering

Department of Electrical & Computer Engineering

Department of Electrical & Computer Engineering

Department of Electrical & Computer Engineering

An over view of sigma delta converters IEEE Signal Processing

Department of Electrical & Computer Engineering

Department of Electrical & Computer Engineering

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