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Address Translation in CAO

Address translation maps virtual addresses used by a program to physical addresses used by the computer's hardware. It can be done statically during program loading or dynamically during execution using a memory management unit. Common techniques for address translation include virtual base addressing using a base address and offset, segmentation using segment tables, and paging using page tables. These tables are typically cached using a translation lookaside buffer to speed up the translation process.

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210 views17 pages

Address Translation in CAO

Address translation maps virtual addresses used by a program to physical addresses used by the computer's hardware. It can be done statically during program loading or dynamically during execution using a memory management unit. Common techniques for address translation include virtual base addressing using a base address and offset, segmentation using segment tables, and paging using page tables. These tables are typically cached using a translation lookaside buffer to speed up the translation process.

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ADDRESS TRANSLATION

Introduction:
-Consider a program, Q which carries
virtual address space, V.
-To execute Q on a particular computer, its
virtual address(V) must be mapped onto
the real address space, R this process is
called as address mapping or address
translation.
-(i.e) Address translation can be viewed as
a function of VR.

ADDRESS TRANSLATION
Cntd..
-In general R-Linear sequence of numbers;
but V is much more complex.
-Address translation can be carried out at
various stages:
1. By the programmer while writing program.
2. By complier during program compilation.
3. By the loader at initial program-load time.
4. By run-time memory management h/w or
s/w.

ADDRESS TRANSLATION
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Types:
Static translation: Address translation can be
completed when the program is first loaded for
execution which is termed as static translation.
Dynamic Translation: Address translation can
be completed during the execution of the
program which is termed as dynamic
translation. This type is desirable and MMUs
are used for this purpose.

ADDRESS TRANSLATION
Virtual Base addressing:
Each and every word used in the program
has its effective address, Aeff which is
specified by base address, B and offset or
displacement, D.
i.e; Aeff = B+D
The effective address may be designed so
that B supplies the higher order bits of A eff
and D supplies the lower order bits.
Aeff = B.D

ADDRESS TRANSLATION
Translation Look-Aside Buffer:

ADDRESS TRANSLATION
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From the figure; the input address Av is a
virtual address consisting of virtual base
address, Bv with a displacement, D.
The real address, BR is stored in a memory
map which is nothing but; BR = f(BV ).
To speed up the process; a part of memory
map is placed in the small high speed
memory of CPU called translation look-aside
buffer.

ADDRESS TRANSLATION
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TLBs input BV of AV
Output Corresponding real address, BR
which should be concatenated with D to get
full physical address AR
If the particular virtual address is not to
TLB, then the part of memory map contains
that particular address is transferred from
external memory to TLB; thus the TLB can
be referred to as address cache.

ADDRESS TRANSLATION
Segments:
The virtual or logical address from the CPU can
be split into segments which consists of logically
related words.
A word in the segment can be referred by a
base(segment) address with a displacement.
If the segments are not available in M1; it will
get transferred from secondary memory, M2
The physical addresses assigned to the
segments are kept in a memory map segment
table.

ADDRESS TRANSLATION
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*Segment descriptor-Burroughs
B6500/7500

ADDRESS TRANSLATION
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Each program has a segment table called
Program Reference Table (PRT).
Each segment can be defined by segment
descriptors.
It contains:
1. A presence bit, P that indicates whether
the segment is present in M1
2. A copy bit, C that specifies whether this is
the original copy of descriptor.

ADDRESS TRANSLATION
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3. A 20-bit size field that specifies the
number of words in segment.
4. A 20-bit address field that is the
segments real address in M1 (if P=1) or
M2 (if P=0)
. A word in segment is specified by the
segment descriptor word in PRT and its
displacement, D.

ADDRESS TRANSLATION
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When P=1, the CPU compares D to the
segment size field Z.
If D>Z D is invalid.
If D<Z D is added to the address
field, S from the descriptor. (i.e) S+D is
the real address.

ADDRESS TRANSLATION
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Advantages:
Efficient use of memory space.
Program segment can be changed or
recompiled without affecting other
segments.
Disadvantages:
Complex allocation is needed as the
size of segment is not fixed.

ADDRESS TRANSLATION
Pages:
A page is a fixed length block that can
be assigned to fixed regions of physical
memory called page frames.
Data transfers will be simplified by
paging.

ADDRESS TRANSLATION
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*Organization of a page table

ADDRESS TRANSLATION
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Each page address has a corresponding
real address of a page frame in M1 (if P=1)
or M2 (if P=0).
If a change is occurred (C=1); that page
must be copied onto the secondary
memory.
Note: Page tables has no information
about block size.

ADDRESS TRANSLATION
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Unusable space between occupied
regions external fragmentation. There
is only a less possibility of external
fragmentation.
Unusable space within the page frame
internal fragmentation.
Paging and segmentation can be
combined to get advantage of both.

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