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Defining Terms

The document summarizes linear delay models for logic gates. It defines propagation delay as being composed of parasitic delay due to intrinsic capacitance and stage effort due to gate complexity and fanout. Logical effort is defined as the ratio of a gate's input capacitance to an inverter's. For example, a NAND gate has a logical effort of 4/3. The parasitic delay of a gate is its delay with zero load and depends on diffusion capacitance. An inverter's normalized parasitic delay is 1, while a NAND or NOR's is 2 times this value. More advanced models like Elmore account for non-linear increases in delay with gate inputs.

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Æshok IncreĐible King
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73 views4 pages

Defining Terms

The document summarizes linear delay models for logic gates. It defines propagation delay as being composed of parasitic delay due to intrinsic capacitance and stage effort due to gate complexity and fanout. Logical effort is defined as the ratio of a gate's input capacitance to an inverter's. For example, a NAND gate has a logical effort of 4/3. The parasitic delay of a gate is its delay with zero load and depends on diffusion capacitance. An inverter's normalized parasitic delay is 1, while a NAND or NOR's is 2 times this value. More advanced models like Elmore account for non-linear increases in delay with gate inputs.

Uploaded by

Æshok IncreĐible King
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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LinearDelayModel

Ingeneralthepropagation
delayofagatecanbewritten
as:d=f+p
pisthedelayduetointrinsic
capacitance.
fistheeffortdelayorstage
effortanddependsonthe
complexityandfanoutofthe
gate.

Thestageeffortis:f=ghwith
thecomplexityrepresentedby
thelogicaleffortg.
Aninverterisdefinedtohavea
logicaleffortof1.

Morecomplexgateshave
greaterlogicaleffortindicating
thattheytakelongertodrivea
givenfanout.
Agatedrivinghidentical
copiesofitselfissaidtohave
anelectricaleffortorfanoutof
h.
Theelectricaleffortofnon
identicalcopiesofthegateor
anytypeofloadiscompounded
tobeh=Cout/Cin.

LogicalEffort
Logicaleffortofagateis
definedastheratiooftheinput
capacitanceofthegatetothe
inputcapacitanceofaninverter
thatcandeliverthesameoutput
current.
AssumingthatthepMOShas
twicetheresistanceofan
nMOSwehaveCin(inv)=3for
inverterthatachieves
symmetricswitching.
Thelogicaleffortofaninverter
is:g=3/3=1.

Howwellcanwedesigna
NANDorNORgatetogivethe
outputcurrentequaltothatofa
unitinverter?
NAND:Cinforunitinverteris
3unitswhilethatoftheNAND
is4unitsforeachinput.
LogicaleffortforNANDis4/3.
TheNORgatehasCinof5
unitsandthushasalogical
effortof5/3.Determinethe
logicaleffortofa3input
NAND

ParasiticDelay
Theparasiticdelayofagateis
thedelayofagatewhenit
driveszeroload.
Aquickestimationofparasitic
delaycomputationsonly
accountsforthediffusion
capacitanceoftheoutputnode.
Theinverterhas3unitsof
diffusioncapacitanceonthe
outputwitheachtransistor
havingresistanceR.
Itsparasiticdelaybecomes3RC

Thenormalizedparasiticdelay
ofaninverteris1andwillbe
referencedaspinv.
pinvistheratiooftheoutput
capacitancetotheinput
capacitance.
Theparasiticdelaysofthe
NANDandNORgatesistwice
thatoftheinverter(2pinv),
becausetheyeachhave6units
ofdiffusioncapacitance.
Notethatinternalnode
capacitanceshavebeenignored.

TheElmoreModel
Parasiticdelaygrowsmorethan
linearlywithanincreaseinthe
numberofinputsinareal
NANDorNORcircuit.
tpd=R(3nC)+Sumn1i=1(iR/n)
(nC)=(n2/2+5n/2)RC
Inpracticeitisadvisableto
keepn=4asseenthattpdgrows
quadraticallywithn.
Seriesntypedevicesarebetter
thanseriesptypedevices.
Why?

Thelinearmodeldoesnot
accountfortheslopesofthe
inputandoutputsignals
(assumeszeroriseandfall
times).
Theinputarrivaltimesisnot
accountedfor.Theinputsdo
notsimultaneouslyswitchON
andOFF.

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