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Partial Scan Testing

This document discusses partial scan testing, which reduces the area overhead of full scan designs by only replacing a subset of flip-flops with scan flip-flops. Key questions for partial scan include which flip-flops to select and how to generate and apply tests. Structural approaches help predictability of test generation for certain circuit classes. These include linear pipeline kernels, balanced kernels, acyclic kernels, and kernels with only self-loops. The s+graph representation is used to select flip-flops for scanning while minimizing area and performance impacts. Partial scan trades off lower fault coverage, longer test times, and less debug support for reduced area overhead compared to full scan.

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pradeep
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97 views

Partial Scan Testing

This document discusses partial scan testing, which reduces the area overhead of full scan designs by only replacing a subset of flip-flops with scan flip-flops. Key questions for partial scan include which flip-flops to select and how to generate and apply tests. Structural approaches help predictability of test generation for certain circuit classes. These include linear pipeline kernels, balanced kernels, acyclic kernels, and kernels with only self-loops. The s+graph representation is used to select flip-flops for scanning while minimizing area and performance impacts. Partial scan trades off lower fault coverage, longer test times, and less debug support for reduced area overhead compared to full scan.

Uploaded by

pradeep
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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PARTIAL SCAN

Gireesh kumar K M
208213004

Partial Scan
Disadvantages of Scan

Additional logic and routing required

Layout area of the circuit is higher

The area overhead associated with full scan can


be reduced by replacing only a subset of the flipflops in a circuit by scan flip-flops. Its called
partial scan.

Key Questions In The Partial-Scan


Methodology

Which flip-flops to select for replacement with


scan flip-flops

To minimize area overhead, the number of flip-flops


selected must be minimum
To reduce performance penalty, selection of flip-flops
that are in critical paths of circuits should be avoided.

How to generate tests for the partial-scan circuit

How to apply tests using partial scan

Kernel

Circuit model obtained by removing flip-flops,


that are selected for partial scan is called
Kernel
To obtain Kernel,
Remove each selected flip-flop FFi from the circuit
State output Yi that drives the D input of the flipflop is the primary output of the kernel
State input yi that is driven by the Q output of the
flip-flop is the primary input of the kernel
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Structural approaches

Test generators cannot guarantee high


fault coverage for Sequential circuits.
For some special classes of sequential
circuits test generation is much more
predictable
And high fault coverage is also possible.
These classes of circuits are characterized
in terms of their sequential structure
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Some definitions

A PATH from a line ci to a line cj is the


sequence of lines starting with ci and ending
with cj
The lines, gates, fanout systems, and flip- flops
via which a path passes are also belong to the
path
Path may pass via one or more flip-flops.
Path that does not pass via any flip-flop Combinational path
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Cyclic path - contains multiple instances of one


or more lines

Acyclic path - no line appears more than once

A sequential circuit is said to be acyclic if all


the paths in the circuit are acyclic

The sequential depth of an acyclic path is the


number of flip-flops in the path

For combinational paths sequential depth is


zero.

The sequential depth of an acyclic sequential


circuit is the maximum of the sequential
depths of the paths in the circuit

s+graph
Directed graph

Used to represent dependency of values at flipflop inputs (state outputs) and primary outputs on
the values at the flip-flop outputs (state inputs)
and primary inputs.

This graph contains,


a node (x ) for each primary input x
i
i
a node (FF ) for each flip-flop FF
i
i
a node (z ) for each primary output z
i
i

Pipelined Kernel

s+graph

Sub-classes of sequential circuits


1)Linear pipeline kernels
2)Balanced kernels
3)Acyclic kernels
4)Kernels with only self-loops

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Linear Pipeline Kernels

If flip-flops can partitioned into sets S1 , S2 , . . . ,


Sl such that

The value at the input of any flip-flop in set S1 depends only


on the values at the primary inputs
For each i, where 2 i l, the value at the input of any flipflop in set Si depends only on the values at the outputs of
flip-flops in set Si1
The value at each primary output depends only on the values
at the outputs of the flip-flops in set Sl

Lengths of all sequential paths are identical

Length is also called the depth of the linear pipeline

Combinational test generator can be used to generate


tests
11

Balanced Kernels

A sequential circuit is said to be balanced if

the circuit is acyclic


all the paths between any given primary input xi
and primary output zj have equal sequential
depths

Combinational test generator can be used


to generate tests for a balanced sequential
kernel

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A Balanced Kernel
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s+graph Cb
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Combinational circuit model Cb*

Obtained by,
1.Remove each flip-flop in the circuit
2.Connect directly the line driving its D input to
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the line driven by its Q output

Acyclic kernels

All paths are acyclic

The s+graph contains no cycles.

Sequential depth of an acyclic kernel is the


maximum of the sequential depth of all its
paths
For an acyclic kernel with sequential depth
d, the test generator needs to consider only
sequences with a maximum of d vectors
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Kernels with only self-loops

s+graphs contain only one type of cycles- selfloops


Self-loop - Cycle formed by the presence of an
edge whose source and destination nodes are
identical
Self-loop indicates that the value at the input of the
flip-flop depends on the value at the output of the
flip-flop - Corresponding circuit is a two-state FSM
Relatively easy to set the state of a two-state FSM,
so test generation is typically easier.
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Selection of flip-flops to scan

The s+graph can be used to select flip-flops to scan for


each of the methodologies.
When a flip-flop FFi is selected for scan, the node
corresponding to FFi is removed from the s+graph
One input node, called FFiI , and one output node,
called FFiO , are added to the s+graph.
All edges that had FFi as their destinations in the
original s+graph now have output node FFiO as their
destination; all the edges that originally had FFi as the
source, now have input node FFiI as their source.

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Advantage

Reduces silicon area overhead

Reduces performance degradation


Disadvantage

lower fault coverage

longer test generation time

less support for debug, diagnosis, and failure


analysis

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THANK YOU

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