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Lecture006. Introduction Systolic Array

systolic array architecture.different type of systolic array architectures are described here.from linear to non linear .systolic arrays are very helpful.

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Shirshendu Roy
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126 views

Lecture006. Introduction Systolic Array

systolic array architecture.different type of systolic array architectures are described here.from linear to non linear .systolic arrays are very helpful.

Uploaded by

Shirshendu Roy
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 36

Systolic

Computing
Fundamentals

What are
Systolic
Arrays?

This is a form of pipelining, sometimes in more than one


dimension.
Machines have been constructed based on this principle,
notable the iWARP, fabricated by Intel.

What are Systolic Arrays?


Laying out algorithms in VLSI

efficient use of hardware


not general purpose
not suitable for large I/O bound applications
control and data flow must be regular
The idea is to exploit VLSI efficiently by laying out
algorithms (and hence architectures) in 2-D (not all systolic
machines are 2-D, but probably most are)

Simple cells
Each cell performs one operation
(usually)

What is Systolic Computing?


Definition 1.
systole (sste-l) noun

The term systolic was first used in this context


by H.T. Kung, then at CMU; it refers to the
pumping action of a heart.

The rhythmic contraction of the heart, especially of the ventricles, by which


blood is driven through the aorta and pulmonary artery after each dilation or
diastole.
[Greek sustol, contraction, from sustellein, to contract. See systaltic.]
systolic (s-stlk) adjective
American Heritage Dictionary

Definition 2.

Data flows from memory in a rhythmic fashion, passing through many


processing elements before it returns to memory.

H.T.Kung

What is Systolic Computing?


Definition 3.
A set of simple processing elements with regular and local
connections which takes external inputs and processes
them in a predetermined manner in a pipelined fashion

Systolic computers are


pumping data in a regular
way
Systolic is normally used to describe the regular pumping action
of the heart
By analogy, systolic computers pump data through
The architectures thus produced are not general but tied to
specific algorithms

Systolic computers have


both pipelining and
parallelism
This is good for computation-intensive tasks but not I/O-intensive
tasks
e.g. signal processing

Most designs are simple and regular in order to keep the VLSI
implementation costs low
programs with simple data and control flow are best

Systolic computers show both pipelining and parallel computation

An SIMD array is a synchronous array


of PEs under the supervision of one
control unit and all PEs receive the
same instruction broadcast from the
control unit but operate on different
data sets from distinct data streams.

What is the difference


between SIMD array
and Systolic array?
Mesh Type SIMD array

Control
Unit

SIMD array usually loads data into its


local memories before starting the
computation.

Control Bus
Processing
Units

Processing
Units

..

Processing
Units

Data Bus
Interconnection Network(Local)

Systolic Array.
Control
Unit
Processing
Units

Control
Unit
Processing
Units

..

Control
Unit
Processing
Units

Interconnection Network(Local)

SIMD array usually loads data into its local memories before starting the
computation.
Systolic arrays usually pipe data from an outside host and also pipe the
results back to the host.

Host Station in Systolic Architecture


used

As a result of the local-communication scheme, a systolic network is easily


extended without adding any burden to the I/O.
I/O

What are the


Structures for
Systolic
Computing?

Systolic Systems increase computing


power for some problems
Systolic computers can be treated as a generalization of
pipelined array architecture.
The Basic Principle of a systolic system.
100ns

Memory
PE

5 MOPS

100ns

Memory
PE PE ----- PE
30 MOPS

NOTE: MOPSMillions of Operations Per Second

What are the functions of a cell in a


Systolic System?
Systolic systems consists of an array of PE(Processing Elements)
processors are called cells,
each cell is connected to a small number of nearest neighbours in a mesh like
topology.

Each cell performs a sequence of operations on data that flows


between them.
Generally the operations are the same in each cell.
Each cell performs an operation or small number of operations on a
data item and then passes it to its neighbor.
Systolic arrays compute in lock-step with each cell (processor)
undertaking alternate compute/communicate phases.

What are the variations of


systolic arrays?
Systolic arrays can be built with variations in:

1. Connection Topology
2D Meshes
hypercubes

2. Processor capability: ranging through:

trivial- just an ALU


ALU with several registers
Simple CPU- registers, run own program
Powerful CPU- local memory also

What are the variations of


systolic arrays?
3. Re-configurable Field programmable Gate Arrays

(FPGAs) offer the possibility that re-programmable, reconfigurable arrays can be constructed to efficiently compute
certain problems.

In general, FPGA technology is excellent for building


small systolic array-style processors.
Special purpose ALUs can be constructed and linked in
a topology, to which the target application maps well.

Regular Interconnect: why good?

What are typical structures of a


Systolic Architecture?
Example of systolic architecture: linear
network

Note the signals going in both directions!

What are typical structures of a


Systolic Architecture?

Early systolic arrays are linear arrays and one dimensional(1D) or two
dimensional I/O(2D).

Most recently, systolic arrays are implemented as planar array with perimeter
I/O to feed data through the boundary.

Linear array with 1D I/O.


This configuration is suitable for single I/O.

1D Linear Array

Linear array with 2D I/O.


It allows more control over
linear array.
Some authors call it
1.5 dimensional
architecture

2D Linear Array

What are typical structures of a


Systolic Architecture?
Example of systolic network: Bi-directional
two-dimensional network

Planar array with perimeter I/O.


This configuration allows
I/O only through its boundary
cells.

Focal Plane array with 3D I/O.


This configuration allows I/O
to each systolic cell.

What are typical structures of a


Systolic Architecture?
Example of systolic network: hexagonal
network

What are typical structures of a


Systolic Architecture?

Example of systolic network:


hypercubes

My experience story:
Hypercubes in Intel

We add with respect to every variable of


dimension. In the example above there
are four variables

What are typical structures of a


Systolic Architecture?
Example of
systolic
network: trees

This architecture can be


used for maximum
independent set and
maximum clique
problems in graph
theory

What are typical structures of a


Systolic Architecture?

3-d Array
4-d Array (mapped to 3-D)
3-D Hex Array
Regular
3-D Trees and Lattices
Interconnect in

3D
This is a research area of our group - look to Perkowskis
and Anas Al Rabadis papers

What are the Applications Of


Systolic Arrays?

Matrix Inversion and Decomposition.


Polynomial Evaluation.
Convolution.
Systolic arrays for matrix multiplication.
Image Processing.
Systolic lattice filters used for speech and seismic signal processing.

Artificial neural network.


Robotics (PSU)
Equation Solving (PSU)
Combinatorial Problems (PSU)

Good topics of a Master Thesis

Discuss General and Soldiers and Symmetric


function Evaluation Problems

Characteristics
of Systolic
Architectures

What are features of Systolic Arrays?


A Systolic array is a computing network possessing the following features:

Synchrony,
Modularity,
Regularity,
Spatial locality,
Temporal locality,
Pipelinability,
Parallel computing.

Synchrony means that the data is rhythmically computed (Timed by a global clock)
and passed through the network.
Modularity means that the array(Finite/Infinite) consists of modular processing units.
Regularity means that the modular processing units are interconnected with
homogeneously.

What are features of Systolic


Arrays?
Spatial Locality means that the cells has a local
communication interconnection.
Temporal Locality means that the cells transmits the signals
from from one cell to other which require at least one unit
time delay.
Pipelinability means that the array can achieve a high speed.

What are the advantages of Systolic


Architectures?
It can be used for special purpose processing architecture
because of
1. Simple and Regular Design.

2. Concurrency and Communication.


3. Balancing Computation with I/O.

The systolic arrays has a regular and simple design (i.e)


They are:

cost effective,
array is modular (i.e) adjustable to various performance goals ,
large number of processors work together,
local communication in systolic array is advantageous for communication
to be faster.

How are the Systolic Processor


attached to general architectures?
A systolic array is used as attached array processor,
it receives data and o/p the results through an attached host computer,
therefore the performance goal of array processor system is a computation
rate that balances I/o bandwidth with host.

With relatively low bandwidth of current I/O devices, to achieve


a faster computation rate it is necessary to perform multiple
computations per I/O access.
Systolic arrays does this efficiently.

What are the advantages of Systolic


Architectures?
Effectively utilize VLSI
Reduce Von Neumann Bottleneck
Target compute-intensive applications
Reduce design cost:
Simple
Regular

Exploit Concurrency

Advantages: Using VLSI Effectively


Replicate simple cells
Local Communication ==>
Short wires
small delay
low clock skew
small drivers
less area

Scalable

Small number of I/Os

Routing costs
dominate: power,
area, and time!

Eliminating the Von Neumans


Bottleneck
Process each input multiple times.
Keep partial results in the PEs.
Does this still present a win today?
Large cost
Many registers

Balancing I/O and Computation


Cant go faster than the data arrives
Reduce bandwidth requirements
Choose applications well!
Choose algorithms correctly!

Exploiting Concurrency
Large number of simple PEs
Manage without instruction store
Methods:
Pipelining
SIMD/MIMD
Vector

Limits application space. How severely?

Sources
1. Seth Copen Goldstein, CMU
2. David E. Culler, UC. Berkeley,
3. [email protected]
4. Syeda Mohsina Afroze
and other students of Advanced Logic Synthesis,
ECE 572, 1999 and 2000.

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