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FPGA Implementation of Fully Parallel LDPC Decoder 2

This document summarizes the implementation of a parallel LDPC encoder and bit flipping decoder. It begins with an overview of digital communication systems and channel coding. It then discusses LDPC codes and presents the architecture of a proposed parallel LDPC encoder. The document also describes a bit flipping decoder algorithm and architecture. It shows simulations of the encoder and decoder in action. In conclusion, it compares the proposed parallel encoder to serial and area-efficient encoder cores.

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97 views36 pages

FPGA Implementation of Fully Parallel LDPC Decoder 2

This document summarizes the implementation of a parallel LDPC encoder and bit flipping decoder. It begins with an overview of digital communication systems and channel coding. It then discusses LDPC codes and presents the architecture of a proposed parallel LDPC encoder. The document also describes a bit flipping decoder algorithm and architecture. It shows simulations of the encoder and decoder in action. In conclusion, it compares the proposed parallel encoder to serial and area-efficient encoder cores.

Uploaded by

harshita
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 36

Implementation of Parallel LDPC

Encoder and Bit FlippingDecoder


Presented by
Pradeep Singh
MTech EX(142080002)
Guided By,
Prof. D. P. Rathod

Basic Communication
system

Fig : Basic Block Diagram of Digital


Communication System
Courtesy : Digital Communication by Simon Haykin, John Wiley
and Son Pub.

Channel Coding Vs Source Coding


Source Encoding efficiently represent Source
information and remove any Redundancies.
Channel Coding reduces error so Bandwidth
and Transmitted Power both can be reduced.
Parameter

Source Encoding

Channel
Coding

Purpose

Compress Information

Reduce Error

Entropy

Reduce Entropy

Increases
Entropy

Channel Coding Types


Algebraic
Channel
Coding

Linear
Block
Codes

Convolutio
nal Codes

Block Codes Vs Convolutional Codes


BER of Block Codes
BER of Convolutional
Codes

BER of Concatenated
Fig:Codes
BER Plot of Different Channe
Codes

Convolutional Codes have good Error Correcting Capability as


compared to Block Codes.
Implementation of Convolutional Codes are difficult as
compared to Block Codes

Courtesy : D Costello, A Comparison Between LDPC Block and


Convolutional Codes , y NSF Grant CCR02- 05310, NASA Grant
NNG05GH73G, and SRC Grant 1170.001

Block Codes Vs Convolutional


Codes

Fig: Comparison of Hardware


Complexity

Courtesy : D Costello, A Comparison Between LDPC Block and


Convolutional Codes , y NSF Grant CCR02- 05310, NASA Grant
NNG05GH73G, and SRC Grant 1170.001

Need For Error Control


Codes
Purpose of Communication system is to efficiently
communicate between sender and Receiver.
Limited Transmission Bandwidth and Transmitted Power.
Eb/No play vital role in communication system as BW
assigned to any operator is always Fixed.
for Fixed Eb/No , all modulation scheme provide finite error
probability.
Error Control code not only reduce error probability but also
reduces Eb/ No. [1]
7

Comparison of LDPC and Turbo


Codes

Fig : Comparison of number of operations with same


number of iteration.
Courtesy : A. Hassan Evaluation of Complexity Versus Performance for
Turbo Code and LDPC Under Different Code Rates, SPACOMM 2012 .
8

LDPC
Low Density Parity Check codes are class of block
codes.
LDPC must have Sparse Matrix i.e. number of 1s
must be less than number of 0s.
General Constraint, Wc << n , Wr << m.
for h - matrix dimension m x n.

10

Encoding of LDPC Codes


Codeword = message bit * G matrix
G- matrix = Transpose(H - Matrix )

13

Decoding

we first compute Syndrome


S=C*H
H = [Pt | I ]
If S = [0] Null matrix then codeword
is error free or else codeword
contain errors. That we compute by
finite iteration and then correct
errors.
14

Without Error Transmission

15

Proposed Encoder

Fig : Block Diagram of Serial LDPC Encoder


17

COMPONENT USED:

SRAM
256*8
XOR GATE
7432X2
AND GATE
7404X2
COUNTER
74LS373
SHIFT REGISTER
54HC9
MICROCONTROLLER AT89C25
18

19

20

Technology Schematic

21

22

Simulation

23

Bit Flipping Decoder Algorithm

Fig: Bit Flipping Decoder Algorithm

Bit Flipping Decoder Architecture

Fig: Bit Flipping Decoder Architecture

Low Power Bit Flipping Decoder


Architecture

Fig : Low Power Bit Flipping Decoder Architecture

RTL of Bit Flipping Decoder


Core in VHDL

Decoding System Simulation in


ISE

In rest system
All Zero input codeword

Test 1: No error in Codeword

Test 4 : Three bit error

Outcome of Project
Area efficient LDPC encoder.
Least Memory requirement for
encoding.
Automatic Memory flushing to save
memory.

32

Comparison
Parameter

Serial Core

Parallel Core

Area Efficient
core

Slice LUT

32

LUT Flip-Flop
pairs

29

Bounded IOs

17

24

10

Speed

Medium

High

Low

Rate

Medium

High

Low

Floor

Medium

High

Low

Future Version of Encoding


Area Efficient version of LDPC
encoder.
Parallel Version of LDPC Encoder.
Fixed Memory for arbitrary message
Count of serial LDPC Decoder.

34

References.
[1] Simon Haykin, Digital Communication System, Wiley Pub., May 2013.
[2]
C.E. Shannon, "A Mathematical Theory of Communication", Bell System
Technical Journal, vol. 27, pp. 379423, 623-656, July, October, 1948.
[3] Sae-Young Chung,G. David Forney, Jr.,Thomas J. Richardson, andRdiger
Urbanke, "On the Design of Low-Density Parity-Check Codes within 0.0045 dB
of the Shannon Limit",pp. 58-60, Feb. 2001. ISSN 1089-7798, IEEE
Communications Letters.
[4] David J. C. MacKay. Information Theory, Inference, and Learning Algorithms
Cambridge: Cambridge University Press, 2003. ISBN 0-521-64298-1.
[5]
S.J. Johnson , Introducing Low-density Parity-check codes, Published
Internal Technical Report , Department of Electrical and Computer
Engineering, University of Newcastle, Australia 0000.
[6]
Robert G. Gallager (1963). Low Density Parity Check Codes (PDF).
Monograph, M.I.T. Press. Retrieved August 7, 2013.
[7] David J.C. MacKay and Radford M. Neal, "Near Shannon Limit Performance of
Low Density Parity Check Codes," Electronics Letters, July 1996
[8] Thomas J. Richardson and M. Amin Shokrollahi and Rdiger L. Urbanke,
"Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes,"
IEEE Transactions in Information Theory, 47(2), February 2001.
35

7/23/16

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