FPGA Implementation of Fully Parallel LDPC Decoder 2
FPGA Implementation of Fully Parallel LDPC Decoder 2
Basic Communication
system
Source Encoding
Channel
Coding
Purpose
Compress Information
Reduce Error
Entropy
Reduce Entropy
Increases
Entropy
Linear
Block
Codes
Convolutio
nal Codes
BER of Concatenated
Fig:Codes
BER Plot of Different Channe
Codes
LDPC
Low Density Parity Check codes are class of block
codes.
LDPC must have Sparse Matrix i.e. number of 1s
must be less than number of 0s.
General Constraint, Wc << n , Wr << m.
for h - matrix dimension m x n.
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Decoding
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Proposed Encoder
COMPONENT USED:
SRAM
256*8
XOR GATE
7432X2
AND GATE
7404X2
COUNTER
74LS373
SHIFT REGISTER
54HC9
MICROCONTROLLER AT89C25
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Technology Schematic
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Simulation
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In rest system
All Zero input codeword
Outcome of Project
Area efficient LDPC encoder.
Least Memory requirement for
encoding.
Automatic Memory flushing to save
memory.
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Comparison
Parameter
Serial Core
Parallel Core
Area Efficient
core
Slice LUT
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LUT Flip-Flop
pairs
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Bounded IOs
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24
10
Speed
Medium
High
Low
Rate
Medium
High
Low
Floor
Medium
High
Low
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References.
[1] Simon Haykin, Digital Communication System, Wiley Pub., May 2013.
[2]
C.E. Shannon, "A Mathematical Theory of Communication", Bell System
Technical Journal, vol. 27, pp. 379423, 623-656, July, October, 1948.
[3] Sae-Young Chung,G. David Forney, Jr.,Thomas J. Richardson, andRdiger
Urbanke, "On the Design of Low-Density Parity-Check Codes within 0.0045 dB
of the Shannon Limit",pp. 58-60, Feb. 2001. ISSN 1089-7798, IEEE
Communications Letters.
[4] David J. C. MacKay. Information Theory, Inference, and Learning Algorithms
Cambridge: Cambridge University Press, 2003. ISBN 0-521-64298-1.
[5]
S.J. Johnson , Introducing Low-density Parity-check codes, Published
Internal Technical Report , Department of Electrical and Computer
Engineering, University of Newcastle, Australia 0000.
[6]
Robert G. Gallager (1963). Low Density Parity Check Codes (PDF).
Monograph, M.I.T. Press. Retrieved August 7, 2013.
[7] David J.C. MacKay and Radford M. Neal, "Near Shannon Limit Performance of
Low Density Parity Check Codes," Electronics Letters, July 1996
[8] Thomas J. Richardson and M. Amin Shokrollahi and Rdiger L. Urbanke,
"Design of Capacity-Approaching Irregular Low-Density Parity-Check Codes,"
IEEE Transactions in Information Theory, 47(2), February 2001.
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