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Fpga Implementation ofa2-DIIR Beam Filter: Siji P.V Aece No:16

This document describes the FPGA implementation of a 2D IIR beam filter. It discusses: 1) The design of a first-order 2D IIR frequency beam filter using a prototype resistively terminated 2D passive network. 2) Implementing the filter using a systolic array architecture of processing cores to achieve high throughput real-time filtering. 3) Verifying the filter works as intended by exciting it with impulse inputs and measuring the response.

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Siji Varghese
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49 views36 pages

Fpga Implementation ofa2-DIIR Beam Filter: Siji P.V Aece No:16

This document describes the FPGA implementation of a 2D IIR beam filter. It discusses: 1) The design of a first-order 2D IIR frequency beam filter using a prototype resistively terminated 2D passive network. 2) Implementing the filter using a systolic array architecture of processing cores to achieve high throughput real-time filtering. 3) Verifying the filter works as intended by exciting it with impulse inputs and measuring the response.

Uploaded by

Siji Varghese
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 36

FPGA

implementation
of a 2-D IIR
beam filter

SIJI P.V
AECE
No:16

ELECTROMAGNETIC
PLANE WAVES IN SPACEConsider
a propagatingTIME
Electromagnetic Wave

Transverse Electric Field -Ey( x, y, z, ct)
Transverse Magnetic field-Hy( x, y, z, ct)
Where
(x,y,z,ct) 4-D space time continuous domain
(x,y,z) 3-D space
t time
c- speed of light in air/ vaccum.

CONTND..
Propagating Electromagnetic waves are 4-D hyper plane
waves in (x,y,z,ct) given by,

In 3D spatial domain (x,y,z) , 4-D space-time plane


waves can be visualized as an infinite set of isoplanes ,each of which is propagating in (x,y,z) over time
t with speed c in a direction normal to the iso-planes.

CONTND.
When a 4-D continuous ST PW signal is received by
a uniform linear array of N sensors, spaced x apart,
it reduces to the 2-D ST PW signal (x,ct) with
spatial direction of arrival (DOA) defined by the
angle between the y axis and the DOA.

2-D SPACE TIME PLANE


WAVES - ROS

Propagating plane wave in


3-D space

2-D spatial view on the


y=0 plane

CONTND..

2-D spatio -temporal DOA

Region of support on 2-D


frequency-domain, aligned
along the spatio -temporal
DOA

SPATIO-TEMPORAL PLANE-WAVE
SIGNALS
Consider a continuous-domain
plane-wave signal

2-D spatio-temporal

Desired 2-D plane wave to be Stopband signal to be


selectively filtered
attenuated by the filter
In discrete-domain, the signal can be represented as

BEAMFORMING
Far field beamforming:
Highly- selective directional enhancement of propagating
spatio -temporal plane waves based on their direction of
arrivals.
Commonly used far field beamformers are

Delay-sum networks
Fractional delay-sum network
2-D Spatio -temporal plane wave
filter

2-D SPACE-TIME PLANE-WAVE


FILTER
Frequency planar beam filter
Simplest 2-d space time plane wave filter.
Passband lies on a line through the origin and ideally
has a beam shaped 2-D passband of uniform width.
The beam-shaped 2-D passband is oriented to enclose
the ROS of the 2-D spectrum while attenuating all
spectra away from this passband.
Can be realized using FIR or IIR digital filters.

CONTND..
Realization using FIR Filters
Stable
For a given selectivity , higher order filters are
required ---- High complexity

For real time implementation ,low complexity


circuits are required ---- IIR beam filter is the
best solution .

First order 2-D IIR frequency


beam plane wave filter
Can be designed from a first-order resistively terminated
passive prototype 2-D network.
Highly selective
Computationally efficient implementation
BIBO stable

CONTND.
The prototype resistively terminated 2-D passive
frequency beam filter
2-D first order continuous domain inductance-resistance
network :

CONTND..
(i) 2-D s-domain transfer function

L1-Passive spatial inductor


L2-Passive temporal inductor
R-passive resistor

(ii) 2-D frequency response transfer function

CONTND..
At frequency-planar resonance:

Equation

of a line in ( ,) space making


and angle - with the -axis.

CONTND..
Therefore
,it is possible

to align the passband of the filter with the ROS of a plane


wave propagating in a certain direction .
To produce a beam pattern over a wide range of frequencies,
owing to the inclination of the passband in ( ,) space.
The selectivity of the pattern provides spatial filtering of
plane waves traveling in directions other than that associated
with the passband.
Such filters can be highly useful in reducing multipath
reflections and broadband interference in communication
system.

CONTND..
(iii) 2-D z-domain transfer function

where the spatio-temporal feedback coefficients are


given by,

CONTND..
(iv) Magnitude frequency response

2-D InputOutput Difference Equation

SYSTOLIC ARRAY ARCHITECTURE


The 2-D space-time input-output direct form difference
equation can be implemented in massively-parallel
systolic array hardware for real-time filtering applications.
Why systolic array architecture?
High-speed plane-wave filtering requires a throughput of
one frame per clock cycle (OFPCC) and very low critical
path (CP) delays for fast real-time operation.
Systolic array architecture has a CP delay of a fraction of
a single multiply-then-add operation and capable of real
time operation at a sustained arithmetic throughput of
OFPCC.

CONTND..
Systolic-arrays are inherently parallel and designed
for high throughputs.
Systolic arrays are modular , regular and locally
interconnected and therefore ideal for VLSI
implementation.
It is stable under finite precision arithmetic.
The processors are free of overflow and temporal
zero - input limit cycle oscillations.
Hence , systolic array architecture is well-suited for
the implementation of real time high throughput
beamforming filters.

CONTND..
(i) Overview of the architecture
()consists of an array of identical parallel processing
core-modules ( PPCMs).
()Each PPCM is capable of producing an output sample
in one clock cycle, therefore leading to a total
throughput of OFPCC.

CONTND..
(ii) Operation
The 2-D difference equation is computed in each
PPCM.
Consider the 2-D difference equation
(1)
Iterate (1) along spatial dimension, starting from the
first spatial location =0,
(2)

CONTND..
The
output at the second spatial location, = 1 is
(3)

Combine (2) and (3) and express the y(1, )as a linear
combination of current and previous inputs and previous
outputs
(4)

CONTND..
to iterate until the last output sample at time
Continue

, at spatial location =N-1, may be expressed as a


linear combination of current inputs, past inputs and
past outputs.
Therefore, all outputs at the spatial sample locations
can be computed simultaneously.

PPCM
Computes (1) in each clock cycle.
PPCM circuit is a multiple-(three)-input single-output
(MISO) 1-D circuit.
The MISO PPCM circuit is derived as follows:
(1) Find y(n1,n2) from the transfer function of the filter.
(i) Transfer function is given as,

CONTND..
(ii)
Find Y(, ) by cross multiplying the terms.

(iii) Take 2-D inverse Z transform

CONTND..
(2) Draw the spatio -temporal signal flow graph (SFG)

CONTND..
(3) Design the PPCM hardware architecture

SYSTOLIC ARCHITECTURE
The systolic array architecture consists of a pipelined
interconnection of identical PPCMs.
Interconnections between PPCMs are independent of
the internal design of the PPCMs.
pipelined
Interconnections
Non-pipelined

NON-PIPELINED INTERCONNECTIONS

Each PPCM is directly connected to adjacent PPCMs

Fig: Spatio -temporal SFG of the systolic array architecture, for =0 , 1, 2

CONTND..
The SFG structure is repeated until =N-1 .
The architecture has good local interconnectivity.
Non-pipelined interconnection of PPCMs is
(generally) too slow for high-speed real-time VLSI
circuit implementation because of the high CP delay

SPEED OPTIMIZATION OF THE


SYSTOLIC ARRAY
ARCHITECTURE

Pipelined interconnections
Inter-PPCM connections employ pipelining to obtain
low propagation delays between PPCM.
Pipelining is achieved by inserting first-in-first-out
(FIFO)s buffers between PPCMs.
Intra-PPCM pipelining.
a) Pipelining for achieving a CP that corresponds
to a single multiplyadd operation
b) LA optimization methods for achieving further
reduction of the CP.

CONTND..

Inter-pipelining

Intra-pipelining

REAL TIME
IMPLEMENTATION
Device to be used: Xilinx Virtex 5 XC5VFX70T1FFG1136 (ML507) FPGA device.
FPGA design tool - Xilinx System Generator (XSG)
Verification
The correct operation of the 2D IIR filter is verified
by exciting the inputs of the filter by a 2-D unit
impulse function and measuring the impulse response
from the onchip realizations

CONCLUSION
Systolic implementation of a 2-D IIR frequency beam
filter transfer function has promising engineering
applications for the directional enhancement of a
propagating broadband space-time plane wave
received on an array of sensors.
systolic array architecture is capable of processing
one frame per clock cycle(OFPCC) and has low CP
(enables high- speed real-time operation).

REFERENCES

THANK YOU

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