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The Scan-Path Technique For Testable Sequential Circuit Design

The scan path technique is a design for testability method introduced in 1975. It allows sequential circuits to be easily set to any internal state and observed through a distinguishing sequence. A modified sequential circuit with scan path properties divides the circuit into a shift register mode and normal mode. It uses a raceless D flip-flop with additional scan in and scan out pins. During testing, the circuit is first set to shift register mode to preset internal states and observe outputs, before switching to normal mode to apply test patterns to combinational logic. While improving testability, the scan path method requires extra circuitry and test time.

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677 views11 pages

The Scan-Path Technique For Testable Sequential Circuit Design

The scan path technique is a design for testability method introduced in 1975. It allows sequential circuits to be easily set to any internal state and observed through a distinguishing sequence. A modified sequential circuit with scan path properties divides the circuit into a shift register mode and normal mode. It uses a raceless D flip-flop with additional scan in and scan out pins. During testing, the circuit is first set to shift register mode to preset internal states and observe outputs, before switching to normal mode to apply test patterns to combinational logic. While improving testability, the scan path method requires extra circuitry and test time.

Uploaded by

Lavanya Bj
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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THE SCAN-PATH

SCAN-PATH TECHNIQUE
TECHNIQUE
THE
FOR TESTABLE
TESTABLE SEQUENTIAL
SEQUENTIAL
FOR
CIRCUIT DESIGN
DESIGN
CIRCUIT
Presented
by,
Presented by,
LavanyashreeB.B.J J
Lavanyashree

INDEX
Sequential circuits
Scan path technique
Modified sequential circuit
Race less D-type flip flop
Configuration of logic card
Advantages and Disadvantages
2

SEQUENTIAL CIRCUITS
Complexity testing sequential circuits due to
feedback loops
Placement of the circuit in a known state.

Timing problems in general

SCAN PATH TECHNIQUE


In 1975, Nippon electric company introduced a design for testability
techniques called SCAN PATH .

Scan is ability to shift into or out of any state


Scan-path design is to reduce test generation complexity for circuit
containing storage devices and feedback path with combinational logic.
The philosophy is to divide & conquer with the purpose to :
1. Set any internal state easily
2. Observe any state through a distinguishing sequence
4

Continued..

Modified general sequential


circuit has following properties:
Circuit can easily be set to
any desired internal state
Circuit has distinguishing
sequence

Fig1: A sequential circuit


5

Continued..

When
C=0 Normal mode
C=1 Shift Register
Uses double throw switch

A
B

Double Throw-Switch has a


contact that can be connected
to either of two other
contacts.

Fig2: A realization for the Doublethrow Switch

Continued..

Procedure for testing circuit is


1. Set C=1 to switch circuit to
shift register mode
2. Check operation as shift register
by scan in inputs ,scan-out
outputs and clock
3. Set initial state of shift register
4. Set C=0 to return to normal
mode
5. Apply test input pattern to
combinational logic
6. Set C=1 ting state to return to
shift register mode
7. Shift out final state while setting
the starting state for the next
test.
8. Go to step 4

Fig3: Modified sequential


circuit
7

Continued..

Raceless D-type flip flop

Scan-out

Normal operation:
C2=1 & C1=0
So data is latched to D1
When C1=1
Output of L1 is latched into L2
Scan in operation:
C2=0
Test input is applied at D2.
When C2=1
Output of L1 is latched into L2

Fig 4: Raceless flip flop with scan path

Continued..

Configuration of Logic card


Here flip flops are connected
as shift register

Scan-out

Scan-in

Each card has one scan path


Nippon electric company
FLT-700 processor.
Fig 5: Configuration of logic card

LVS07,VLSI &EMBEDDED SYSTEMS

Advantages and Disadvantages


Advantages:
Design automation
High fault coverage; helpful in diagnosis
Easy to generate test pattern

Disadvantages:
Large test data volume and long test time
Requires extra pins or gates for transformation

10

THANK YOU..
11

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