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The Scan-Path Technique For Testable Sequential Circuit Design

This document discusses the scan path technique for designing testable sequential circuits. The scan path technique modifies sequential circuits by adding a scan mode where flip flops are connected as a shift register, allowing the circuit to be set to any internal state. In scan mode, a test input can be shifted into the circuit and the internal state can be shifted out. This allows the circuit to be easily tested by setting inputs, running tests, and observing outputs. Key aspects of the scan path technique include using raceless D flip flops and connecting flip flops on logic cards into a shift register for scan testing. While the technique improves testability, it also increases test data volume and circuit complexity.

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Lavanya Bj
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2K views11 pages

The Scan-Path Technique For Testable Sequential Circuit Design

This document discusses the scan path technique for designing testable sequential circuits. The scan path technique modifies sequential circuits by adding a scan mode where flip flops are connected as a shift register, allowing the circuit to be set to any internal state. In scan mode, a test input can be shifted into the circuit and the internal state can be shifted out. This allows the circuit to be easily tested by setting inputs, running tests, and observing outputs. Key aspects of the scan path technique include using raceless D flip flops and connecting flip flops on logic cards into a shift register for scan testing. While the technique improves testability, it also increases test data volume and circuit complexity.

Uploaded by

Lavanya Bj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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THE SCAN-PATH

SCAN-PATH TECHNIQUE
TECHNIQUE
THE
FOR TESTABLE
TESTABLE SEQUENTIAL
SEQUENTIAL
FOR
CIRCUIT DESIGN
DESIGN
CIRCUIT
Presented by,
Presented by,
Lavanyashree B. J
Lavanyashree B. J
LVS07
LVS07
VLSI Design & Embedded Systems
VLSI Design & Embedded Systems

INDEX
Combinational and sequential circuits
Scan path technique
Modified sequential circuit
Raceless D-type flip flop
Configuration of logic card
Advantages and Disadvantages
LVS07,VLSI &EMBEDDED SYSTEMS

COMBINATIONAL AND SEQUENTIAL


CIRCUITS
Complexity testing sequential circuits due to
feedback loops
Placement of the circuit in a known state.

Timing problems in general

LVS07,VLSI &EMBEDDED SYSTEMS

SCAN PATH TECHNIQUE


In 1975, Nippon electric company introduced a design for testability
techniques called SCAN PATH .

Scan is ability to shift into or out of any state


Scan-path design is to reduce test generation complexity for circuit
containing storage devices and feedback path with combinational logic.
The philosophy is to divide & conquer with the purpose to :
1. Set any internal state easily
2. Observe any state through a distinguishing sequence
LVS07,VLSI &EMBEDDED SYSTEMS

Continued..

Modified general sequential


circuit has following properties:
Circuit can easily be set to
any desired internal state
Circuit has distinguishing
sequence

Fig1: A sequential circuit


LVS07,VLSI &EMBEDDED SYSTEMS

Continued..

When
C=0 Normal mode
C=1 Shift Register
Uses double throw switch

A
B

Double Throw-Switch has a


contact that can be connected
to either of two other
contacts.

LVS07,VLSI &EMBEDDED SYSTEMS

Fig2: A realization for the Doublethrow Switch

Continued..

Procedure for testing circuit is


1. Set C=1 to switch circuit to
shift register mode
2. Check operation as shift register
by scan in inputs ,scan-out
outputs and clock
3. Set initial state of shift register
4. Set C=0 to return to normal
mode
5. Apply test input pattern to
combinational logic
6. Set C=1 ting state to return to
shift register mode
7. Shift out final state while setting
the starting state for the next
test.
8. Go toLVS07,VLSI
step 4&EMBEDDED SYSTEMS

Fig3: Modified sequential


circuit
7

Continued..

Raceless D-type flip flop

Scan-out

Normal operation:
C2=1 & C1=0
So data is latched to D1
When C1=1
Output of L1 is latched into L2
Scan in operation:
C2=0
Test input is applied at D2.
When C2=1
Output of L1 is latched into L2

Fig 4: Raceless flip flop with scan path

LVS07,VLSI &EMBEDDED SYSTEMS

Continued..

Configuration of Logic card


Here flip flops are connected
as shift register

Scan-out

Scan-in

Each card has one scan path.

Fig 5: Configuration of logic card

LVS07,VLSI &EMBEDDED SYSTEMS

Advantages and Disadvantages


Advantages:
Design automation
High fault coverage; helpful in diagnosis
Easy to generate test pattern

Disadvantages:
Large test data volume and long test time
Requires extra pins or gates for transformation

LVS07,VLSI &EMBEDDED SYSTEMS

10

THANK YOU..
LVS07,VLSI &EMBEDDED SYSTEMS

11

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