Introduction to VLSI Circuits and

Systems

Chapter 09

Advanced Techniques in CMOS Logic

Circuits

Dept. of Electronic Engineering

National Chin-Yi University of Technology
Fall 2007

Introduction to VLSI Circuits and Systems, NCUT

Outline

Mirror Circuits
Pseudo-nMOS
Tri-State Circuits
Clocked CMOS
Dynamic CMOS Logic Circuits
Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT

Mirror Circuits

Mirror circuits are based on series-parallel logic gates,

but are usually faster and have a more uniform layout
Output 0s imply that an nFET chain is conducting to

ground
Output 1s means that a pFET group provides support from
the power supply
(a) Circuit

Figure 9.1 XOR function table

(b) Layout
Figure 9.2 XOR mirror circuit
Introduction to VLSI Circuits and Systems, NCUT

XOR & XNOR

The advantages of the mirror circuit are

more symmetric layouts and shorter rise
and fall times

In Figure 9.3, transient calculations of

XOR
x C out (2 R x ) C x R x

(9.1)

where x is p or n

t r 2.2 p

(9.2)

t f 2.2 n

(9.3)

Figure 9.3 Switching mode

for transient calculations
(XOR)

In Figure 9.4, a example of XNOR

a b a b a b

(9.4)

Figure 9.4 Exclusive-NOR (XNOR) circuit

Introduction to VLSI Circuits and Systems, NCUT

Outline

Mirror Circuits
Pseudo-nMOS
Tri-State Circuits
Clocked CMOS
Dynamic CMOS Logic Circuits
Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT

Pseudo-nMOS

Adding a single pFET to otherwise nFET-only circuit

produces a logic family that is called pseudo-nMOS
Less transistor than CMOS
For N inputs, only requires (N+1) FETs
Pull-up device: pFET is biased active since the grounded

gate gives VSGp = VDD

Pull-down device: nFET logic array acts as a large switch

between the output f and ground

However, since the pFET is always biased on, VOL can
never achieve the ideal value of 0 V

Figure 9.5 General

structure of a pseudonMOS logic gate

A simple inverter using pseudo-nMOS as Figure 9.6

n
2
2VDD VTn VOL VOL p VDD VTp
2
2
VOL VDD VTn

VDD VTn 2

p
V VTp
n DD

(9.4)

(9.5)
Figure 9.6 Pseudo-nMOS inverter
Introduction to VLSI Circuits and Systems, NCUT

nFET Array in PseudonMOS

The design of nFET array of pseudo-nMOS is the

same as in standard CMOS
Series and parallel logic FETs
Smaller simpler layouts, and interconnect is much simpler
However, the sizes need to be adjusted to insure proper

electrical coupling to the next stage

Resize in physical design

(a) NOR2

(b) NAND2

Figure 9.7 Pseudo-nMOS NOR and NAND

gates

(a) General
circuit

(b)
Layout
Figure 9.8 AOI gate
Introduction to VLSI Circuits and Systems, NCUT

Outline

Mirror Circuits
Pseudo-nMOS
Tri-State Circuits
Clocked CMOS
Dynamic CMOS Logic Circuits
Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT

Tri-State Circuits

A tri-state circuit produces the usual 0 and 1

voltages, but also has a third high impedance Z (or
Hi-Z)
Useful for isolating circuits from common bus lines
In Hi-Z case, the output capacitance can hold a voltage

even though n hardwire connection exists

A non-inverting circuit ( a buffer) can be obtained by

adding a regular static inverter to the input

(b) CMOS
(a) Symbol and
circuit
operation
Figure 9.9 Tri-state

Figure 9.10 Tri-state

layout
Introduction to VLSI Circuits and Systems, NCUT

Outline

Mirror Circuits
Pseudo-nMOS
Tri-State Circuits
Clocked CMOS
Dynamic CMOS Logic Circuits
Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT

Clock-CMOS (C2MOS)

Static CMOS: the output of a static logic gate is

valid so long as the input value are valid and the
circuit has stabilized

However, logic delays are due to the rippling

through the circuits
Not reference to any specific time base
So on, Clock CMOS, or C2MOS is proposed

C2MOS concept: non-overlapping clock

t t 0

(9.9)

t VDD t

(9.10)

Figure 9.11 Clock

signals

But in physical signal, the clocks may overlap slightly

during a transition
Introduction to VLSI Circuits and Systems, NCUT

C2MOS Networks

C2MOS is composed of a static logic circuit with tri-state output network

(made up of FETs M1 and M2) that is controlled by and
When

gate
When

0 , both M1 and M2 are active, and become to a standard static logic

1
, both M1 and M2 are cutoff, so the output is a Hi-Z state

Figure 9.12 Structure of a C2MOS

gate
Introduction to VLSI Circuits and Systems, NCUT

Example of C2MOS

(a) NAND2

(a) Inverter

(b) NOR2
Figure 9.13 Example of C2MOS logic gate

(b) NAND2

Figure 9.14 Layout examples of C2MOS

circuits
Introduction to VLSI Circuits and Systems, NCUT

Leakage in C2MOS (1/2)

Charge leakage: since the output node cannot hold

the charge on Vout very long
This places a lower limit on the allowable clock

frequency

If a voltage is applied to the drain or source, a small

leakage current flows into, or out of, the device
One reason is due to the required bulk connections

(a) Bulk leakage currents

The current off of the capacitor by iout

iout in i p

(9.11)

Cout

dV
dt

I L Cout

dV
dt

(9.12)

IL
dt
0 C
out

(9.13)

IL
t
Cout

(9.14)

V (t )

dV

V1

V (t ) V1

(b) Logic 1 voltage decay

Figure 9.15 Charge leakage
problem
Introduction to VLSI Circuits and
Systems, NCUT

Leakage in C2MOS (2/2)

IL
Cout

V (th ) V1

th Vx

C
th out (V1 Vx )
IL
50 10 15
(1) 0.5 sec
13
10

t h

IL
Cout

V (t )

W
L

(9.15)
(9.16)
(9.17)
(9.18)

(a) Bulk leakage currents

(V V ) /( nVth )
e GS T

(9.19)

50 1515
(1) 50 sec
9
10

(9.20)

50 1515
(1) 0.5 sec
7
10

(9.21)

I I D0

t h
th

I L (V ) Cout (V )
t

V (t )

Vx

dt

dV
dt

Cout (V )
dV t
I L (V )

(9.22)
(9.23)

(b) Logic 1 voltage decay

Figure 9.15 Charge leakage
Introduction to VLSIproblem
Circuits and Systems, NCUT

Outline

Mirror Circuits
Pseudo-nMOS
Tri-State Circuits
Clocked CMOS
Dynamic CMOS Logic Circuits
Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT

Dynamic CMOS Logic Circuits

(1/2)

A dynamic logic gate uses clocking and charge storage

properties of MOSFETs to implement logic operations
Provide a synchronized data flow
Result is valid only for a short period of time
Less transistors, and may be faster than static cascades

Based on the circuit in Figure 9.17

The clock drives a complementary pair of transistors M n

and Mp
An nFET array between the output node and ground to

perform the logic function

When 0 , it is called precharge phase
When 1 , it is called evaluation phase
Figure 9.17 Basic dynamic logic
gate
Introduction to VLSI Circuits and Systems, NCUT

Dynamic CMOS Logic Circuits

(2/2)

A dynamic NAND3 is shown in Figure 9.18

f a bc

(9.24)

When f = 1, charge leakage reduces the voltages held on the output node

Figure 9.18 Dynamic logic gate

example

Introduction to VLSI Circuits and Systems, NCUT

Charge Sharing Problem

The origin of the charge sharing problem is the

parasitic node capacitance C1 and C2 between FETs
When clock

, and the capacitor voltage V1 and V2

1 time, the total charge is
are both 0 V at
this

Q CoutVDD
(9.25)
The worst-case charge
sharing
condition is when the

inputs are at (a, b, c) = (1, 1, 0)

Vout V2 V1 V f (9.26) (When the current flow ceases) Figure 9.19 Charge sharing
The principle of conservation of charge
circuit
Q CoutV f C1V f C2V f
(Cout C1 C2 )V f

(9.27)

Cout

Cout
1
C1 C2

(9.30)

Q (Cout C1 C2 )V f CoutVDD

(9.28)

V f VDD

(9.31)

Cout
VDD
V f
C

C
1
2
out

(9.29)

Cout C1 C2

(9.32)

Introduction to VLSI Circuits and Systems, NCUT

Domino Logic (1/2)

Domino logic is a CMOS logic style obtained by

adding a static inverter to the output of the basic
dynamic gate circuit
Non-inverting
Cascade operation
Domino chain reaction that must start at the first

stage and then propagate stage by stage to the output

(a) AND gate

Figure 9.20 Domino logic

stage

(b) OR gate

Figure 9.21 Non-inverting domino logic

gates

Figure 9.22 Layout

for domino AND gate

Introduction to VLSI Circuits and Systems, NCUT

Domino Logic (2/2)

Note that the operation indicates that domino gates are only useful in cascades

Figure 9.23 A domino cascade

(a) Single-FET charge

(b) Feedback controlled
keeper
keeper
Figure 9.25 Charge-keeper
circuits

f1 G
f2 F G
(a) Percharge

(9.33)

(b) Evaluate

Figure 9.24 Visualization of the domino

effect

Figure 9.26 Structure of a MODL

circuit

Introduction to VLSI Circuits and Systems, NCUT

Outline

Mirror Circuits
Pseudo-nMOS
Tri-State Circuits
Clocked CMOS
Dynamic CMOS Logic Circuits
Dual-Rail Logic Networks

Introduction to VLSI Circuits and Systems, NCUT

Dual-Rail Logic Networks

Single-rail logic: the value of a variable is either a 0 or a 1 only

Dual-rail logic: both the variable x and its complement x are used to form
the difference
f x ( x x)

(9.35)

df x dx d x

dt dt dt

(9.36)

dx
dx

dt
dt

(9.37)

df x
dx
2
dt
dt

(9.38)

Introduction to VLSI Circuits and Systems, NCUT

Differential Cascode Voltage

Switch Logic, DCVS (1/2)

DCVS or differential CVSL (CVSL) provides for

dual-rail logic gates, and the out results f and f
are held until the inputs induce a change

(a) AND/NAND

Figure 9.27 Structure of a CVSL logic

gate

(b) OR/NOR
Figure 9.28 CVSL gate
example

Introduction to VLSI Circuits and Systems, NCUT

Complementary Pass-Transistor Logic

Complementary Pass-Transistor (CPL): an

dual-rail tech. that is based on nFET logic
equations
f a b a a

(9.41)

a b a a b a b

(9.42)

(a) AND gate

(b) AND/NAND array

Figure 9.32 CPL AND/NAND circuit

CPL has several 2-input gates that can be

created by using the same transistor topology
with different input sequences

Less layout area

However, threshold will be loss and the fact that
an input variable may have to drive more than
one FET terminal
(a) OR/NOR

(b) XOR/XNOR

Figure 9.33 2-input CPL

arrays

Introduction to VLSI Circuits and Systems, NCUT