CMOS VLSI DESIGN

A SYSTEMS & CIRCUITS

PERSPECTIVE

A BRIEF HISTORY
In 2008, Intels Itanium microprocessor contained more than 2
billion transistors and a 16 Gb Flash memory contained more
than 4 billion transistors.
This corresponds to a compound annual growth rate of 53%
over 50 years. No other technology in history has sustained
such a high growth rate lasting for so long.
This incredible growth has come from steady miniaturization of
transistors and improvements in manufacturing processes.
Most other fields of engineering involve tradeoffs between
performance, power, and price. However, as transistors
become smaller, they also become faster, dissipate less power,
and are cheaper to manufacture.
This synergy has not only revolutionized electronics, but also
society at large.

 The processing performance once dedicated to secret

government supercomputers is now available in
disposable cellular telephones. The memory once
needed for an entire companys accounting system is
now carried by a teenager in her iPod.
Improvements in integrated circuits have enabled
space exploration, made automobiles safer and more
fuelefficient, revolutionized the nature of warfare,
brought much of mankinds knowledge to our Web
browsers, and made the world a flatter place

 Annual sales in the worldwide semiconductor market.

Integrated circuits became a $100 billion/year business in
1994. In 2007, the industry manufactured approximately 6
quintillion (6 1018) transistors, or nearly a billion for
every human being on the planet. Thousands of engineers
have made their fortunes in the field. New fortunes lie
ahead for those with innovative ideas and the talent to
bring those ideas to reality.
During the first half of the twentieth century, electronic
circuits used large, expensive, power-hungry, and unreliable
vacuum tubes. In 1947, John Bardeen and Walter Brattain
built the first functioning point contact transistor at Bell
Laboratories, shown in Figure . It was nearly classified as a
military secret, but Bell Labs publicly introduced the device
the following year.

Story of a Transistor
We have called it the Transistor, T-R-A-NS-I-S-T-O-R, because it is a resistor or
semiconductor device which can amplify
electrical signals as they are transferred
through it from input to output terminals.
It is, if you will, the electrical equivalent of
a vacuum tube amplifier. But there the
imilarity ceases. It has no vacuum, no
filament, no glass tube. It is composed
entirely of cold, solid substances.

 Ten years later, Jack Kilby at Texas Instruments realized the potential for
miniaturization if multiple transistors could be built on one piece of silicon.
Figure shows his first prototype of an integrated circuit, constructed from a
germanium slice and gold wires.
The invention of the transistor earned the Nobel Prize in Physics in 1956 for
Bardeen, Brattain, and their supervisor William Shockley. Kilby received the
Nobel Prize in Physics in 2000 for the invention of the integrated circuit.
Transistors can be viewed as electrically controlled switches with a control
terminal and two other terminals that are connected or disconnected
depending on the voltage or current applied to the control. Soon after inventing
the point contact transistor, Bell Labs developed the bipolar junction transistor.
Bipolar transistors were more reliable, less noisy, and more power-efficient.
Early integrated circuits primarily used bipolar transistors.
Bipolar transistors require a small current into the control (base) terminal to
switch much larger currents between the other two (emitter and collector)
terminals. The quiescent power dissipated by these base currents, drawn even
when the circuit is not switching,

 limits the maximum number of transistors that can be integrated onto a single die. By the 1960s,
Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) began to enter production. MOSFETs
offer the compelling advantage that they draw almost zero control current while idle. They come in
two flavors: nMOS and pMOS, using n-type and p-type silicon, respectively. The original idea of field
effect transistors dated back to the German
scientist Julius Lilienfield in 1925 [US patent 1,745,175] and a structure closely resembling the
MOSFET was proposed in 1935 by Oskar Heil [British patent 439,457], but materials problems foiled
early attempts to make functioning devices.
In 1963, Frank Wanlass at Fairchild described the first logic gates using MOSFETs [Wanlass63].
Fairchilds gates used both nMOS and pMOS transistors, earning the name Complementary Metal
Oxide Semiconductor, or CMOS. The circuits used discrete transistors but consumed only nanowatts
of power, six orders of magnitude less than their bipolar counterparts. With the development of the
silicon planar process, MOS integrated circuits became attractive for their low cost because each
transistor occupied less area and the fabrication process was simpler [Vadasz69]. Early commercial
processes used only pMOS transistors and suffered from poor performance, yield, and reliability.
Processes using nMOS transistors became common in the 1970s [Mead80].
Intel pioneered nMOS technology with its 1101 256-bit static random access memory and 4004 4-bit
microprocessor, as shown in Figure 1.3. While the nMOS process was less expensive than CMOS,
nMOS logic gates still consumed power while idle. Power consumption became a major issue in the
1980s as hundreds of thousands of transistors were integrated onto a single die. CMOS processes
were widely adopted and have essentially replaced nMOS and bipolar processes for nearly all digital
logic applications.

 In 1965, Gordon Moore observed that plotting the number

of transistors that can be most economically manufactured
on a chip gives a straight line on a semilogarithmic scale
[Moore65]. At the time, he found transistor count doubling
every 18 months.
This observation has been called Moores Law and has
become a self-fulfilling prophecy. Figure 1.4 shows that the
number of transistors in Intel microprocessors has doubled
every 26 months since the invention of the 4004. Moores
Law is driven primarily by scaling down the size of
transistors and, to a minor extent, by building larger chips.
The level of integration of chips has been classified as
small-scale, medium-scale, large-scale, and very largescale.

Transistors in Intel
Microprocessors

 Small-scale integration (SSI) circuits, such as the 7404 inverter, have fewer
than 10
gates, with roughly half a dozen transistors per gate. Medium-scale
integration (MSI) circuits, such as the 74161 counter, have up to 1000
gates.
Large-scale integration (LSI) circuits, such as simple 8-bit microprocessors,
have up to 10,000 gates. It soon became apparent that new names would
have to be created every five years if this naming trend continued and thus
the term very large-scale integration (VLSI) is used to describe most
integrated circuits from the 1980s onward.

A corollary of Moores law is Dennards Scaling Law [Dennard74]: as

transistors shrink, they become faster, consume less power, and are
cheaper to manufacture. Figure 1.5 shows that Intel microprocessor clock
frequencies have doubled roughly every 34 months.
This frequency scaling hit the power wall around 2004, and clock
frequencies have leveled off around 3 GHz. Computer performance,
measured in time to run an application, has advanced even more than raw
clock speed. Presently, the performance is driven by the number of cores on
a chip rather than by the clock.
Even though an individual CMOS transistor uses very little energy each time

The feature size of a CMOS manufacturing process refers to the minimum

dimension of a transistor that can be reliably built. The 4004 had a feature
size of 10micro m in 1971. The Core 2 Duo had a feature size of 45 nm in
2008. Manufacturers introduce a new process generation (also called a
technology node) every 23 years with a 30% smaller feature size to pack
twice as many transistors in the same area. Figure 1.6 shows the
progression of process generations.
Feature sizes down to 0.25 micro m are generally specified in microns (10
6 m), while smaller feature sizes are expressed in nanometers (109 m).
Effects that were relatively minor in micron processes, such as transistor
leakage, variations in characteristics of adjacent transistors, and wire
resistance, are of great significance in nanometer processes.
Moores Law has become a self-fulfilling prophecy because each company
must keep up with its competitors. Obviously, this scaling cannot go on
forever because transistors cannot be smaller than atoms. Dennard scaling
has already begun to slow.

Clock frequencies of Intel

microprocessors

Processor generations

 By the 45 nm generation, designers are having to make trade-offs

between improving power and improving delay. Although the cost
of printing each transistor goes down, the one-time design costs
are increasing exponentially, relegating state-of-the-art processes
to chips that will sell in huge quantities or that have cutting-edge
performance requirements.
However, many predictions of fundamental limits to scaling have
already proven wrong. Creative engineers and material scientists
have billions of dollars to gain by getting ahead of their
competitors. In the early 1990s, experts agreed that scaling
would continue for at least a decade but that beyond that point
the future was murky. In 2009, we still believe that Moores Law
will continue for at least another decade.
The future is yours to invent.

MOS transistors
Each transistor consists of a stack of
the conducting gate, an insulating
layer of silicon dioxide (SiO2, better
known as glass), and the silicon
wafer, also called the substrate, body,
or bulk.
Gates of early transistors were built
from metal, so the stack was called
metaloxide- semiconductor, or MOS

 Since the 1970s, the gate has been formed from

polycrystalline silicon (polysilicon), but the name
stuck. (Interestingly, metal gates reemerged in
2007 to solve materials problems in advanced
manufacturing processes.) An nMOS transistor
is built with a p-type body and has regions of ntype semiconductor adjacent to the
gate called the source and drain.
They are physically equivalent and for now we
will regard them as interchangeable. The body is
typically grounded.

PMOS
A pMOS transistor is just the
opposite, consisting of p-type source
and drain regions with an n-type
body. In a CMOS technology with
both flavors of transistors, the
substrate is either n-type or p-type.
The other flavor of transistor must be
built in a special well in which dopant
atoms have been added to form the
body of the opposite type.

 The gate is a control input: It affects the flow of

electrical current between the source and drain.
Consider an nMOS transistor.
The body is generally grounded so the pn
junctions
of the source and drain to body are reverse-biased.
If the gate is also grounded, no current flows
through the reverse-biased junctions. Hence, we say
the transistor is OFF.
If the gate voltage is raised, it creates an electric
field that starts to attract free electrons to the
underside of the SiSiO2 interface.

 If the voltage is raised enough, the

electrons outnumber the holes and a
thin region under the gate called the
channel is inverted to act as an ntype semiconductor.
Hence, a conducting path of electron
carriers is formed from source to
drain and current can flow. We say
the transistor is ON.

 For a pMOS transistor, the situation is

again reversed. The body is held at a
positive
voltage. When the gate is also at a
positive voltage, the source and
drain junctions are
reverse-biased and no current flows,
so the transistor is OFF.

 When the gate voltage is lowered, positive

charges are attracted to the underside of
the SiSiO2 interface.
A sufficiently low gate voltage inverts the
channel and a conducting path of positive
carriers is formed from source to drain, so
the transistor is ON. Notice that the symbol
for the pMOS transistor has a bubble on
the gate, indicating that the transistor
behavior is the opposite of the nMOS.

 The positive voltage is usually called VDD

or POWER and represents a logic 1 value in
digital circuits.
In popular logic families of the 1970s and
1980s, VDD was set to 5 volts.
Smaller, more recent transistors are unable
to withstand such high voltages and have
used
supplies of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
1.0 V, and so forth.

 The low voltage is called GROUND

(GND) or VSS and represents a logic
0. It is normally 0 volts.

 In summary, the gate of an MOS

transistor controls the flow of current
between the source and drain.
Simplifying this to the extreme
allows the MOS transistors to be
viewed as simple ON/OFF switches.

 When the gate of an nMOS transistor

is 1, the transistor is ON and there is
a conducting path from source to
drain.
When the gate is low, the nMOS
transistor is OFF and almost zero
current flows from source to drain.

 A pMOS
transistor is just the opposite, being ON
when the
gate is low and OFF when the gate is high.
This
switch model is illustrated in Figure 1.10,
where g, s, and d indicate gate, source, and
drain. This model will be our most common
one when discussing circuit behavior.

CMOS LOGIC
THE INVERTER:
Figure shows the schematic and symbol for a CMOS
inverter or NOT gate using one nMOS transistor and
one pMOS transistor.
The bar at the top indicates VDD and the triangle at
the bottom indicates GND. When the input A is 0, the
nMOS transistor is OFF and the pMOS transistor is ON.
Thus, the output Y is pulled up to 1 because it is
connected to VDD but not to GND. Conversely, when
A is 1, the nMOS is ON, the pMOS is OFF, and Y is
pulled down to 0. This is summarized in Table

 Figure 1.12(a) shows a 2-input CMOS NAND gate. It consists of two series nMOS
transistors
between Y and GND and two parallel pMOS transistors between Y and VDD. If
either input A or B is 0, at least one of the nMOS transistors will be OFF, breaking
the
path from Y to GND. But at least one of the pMOS transistors will be ON, creating a
path from Y to VDD. Hence, the output Y will be 1. If both inputs are 1, both of the
nMOS
transistors will be ON and both of the pMOS transistors will be OFF. Hence, the
output
will be 0. The truth table is given in Table 1.2 and the symbol is shown in Figure
1.12(b).
Note that by DeMorgans Law, the inversion bubble may be placed on either side of
the
gate. In the figures in this book, two lines intersecting at a T-junction are
connected. Two
lines crossing are connected if and only if a dot is shown

k-input NAND gates are constructed using k series nMOS

transistors and k parallel pMOS transistors. For example, a 3input NAND gate is shown in Figure 1.13. When any of the inputs
are 0, the output is pulled high through the parallel pMOS
transistors. When all of the inputs are 1, the output is pulled low
through the series nMOS transistors.

CMOS Logic Gates

The inverter and NAND gates are examples
of static CMOS logic gates, also called
complementary CMOS gates.
In general, a static CMOS gate has an
nMOS pull-down network to connect the
output to 0 (GND) and pMOS pull-up
network to connect the output to 1 (VDD),
as shown in Figure 1.14.
The networks are arranged such that one is
ON and the other OFF for any input pattern.

 The pull-up and pull-down networks

in the inverter each consist of a
single transistor. The NAND gate uses
a series pull-down network and a
parallel
pull-up
network.
More
elaborate networks are used for
more complex gates. Two or more
transistors in series are ON only if all
of the series transistors are ON.

 Two or more transistors in parallel are ON

if any of the parallel transistors are ON.
This is illustrated in Figure 1.15 for nMOS
and pMOS transistor pairs.
By using combinations of these
constructions, CMOS combinational gates
can be constructed. Although such static
CMOS gates are most widely used.

 In general, when we join a pull-up network

to a pull-down network to form a logic gate
as shown in Figure 1.14, they both will
attempt to exert a logic level at the output.
The possible levels at the output are
shown in Table 1.3.
From this table it can be seen that the
output of a CMOS logic gate can be in four
states.

 The 1 and 0 levels have been encountered with the

inverter and NAND gates, where either the pull-up or
pull-down is OFF and the other structure is ON.
When both pull-up and pull-down are OFF, the high
impedance or floating Z output state results.
This is of importance in multiplexers, memory elements,
and tristate bus drivers.
The crowbarred (or contention) X level exists when both
pull-up and pull-down are simultaneously turned ON.
Contention between the two networks results in an
indeterminate output level and dissipates static power. It
is usually an unwanted condition.

The NoR GATE

A 2-input NOR gate is shown in
Figure The nMOS transistors are in
parallel to pull the output low when
either input is high.
The pMOS transistors are in series to
pull the output high when both inputs
are low, as indicated in Table.
The output is never crowbarred or
left floating.

 Example 1.1
Sketch a 3-input CMOS NOR gate.