System on Chip (SoC)

Design

Outline
Key Trends and The SoC Paradigm
System on Chip
Architecture
Design
Cores
Interconnection
Cost Benefits of SoC
Examples
Conclusion

Moores Law and Technology Scaling

the performance of an IC, including the number components on it, doubles

every 18-24 months with the same chip price ... - Gordon Moore - 1960

The Productivity Gap

Silicon technology roadmap

intrinsic capability of ICs (transistor count / gate delay)
grows with ~ 50% per year (Moores Law)
power limits the performance
low power SoC
gate length (nm)
supply voltage
transistor count (M)
chip size (mm2)
clock frequency (GHz)
wiring levels
max power (W)

2001
130
1.2
3.3
100
0.15
6
0.1

2004
90
1
8.3
120
0.3
7
0.1

2010
45
0.6
40
144
0.6
9
0.1

high performance
MPU/SoC
2001
2004 2010
90
53
25
1.1
1
0.6
276
553
2212
310
310
310
1.7
2.4
4.7
7
8
10
130
160
218

Introduction - History
First generation chips contained a few transistors.
Today, silicon technology allows us to build chips consisting of
hundreds of millions of transistors (Intel Pentium IV: 0.09
micron). This technology has enabled new levels of system
integration onto a single chip.
Mobile phones, portable computers and Internet appliances will
be built using a single chip.
The demand for more powerful products and the huge capacity
of today s silicon technology have moved System-on-Chip (SoC)
designs from leading edge to mainstream design practice.
System on Chip (SoC) technology will put the maximum
amount of technology into the smallest possible space.

Electronic systems
Systems on chip are everywhere

Technology advances enable increasingly more complex designs

Central Question: how to exploit deepsubmicron technologies efficiently?

Main Challenges of Wireless Sensor Network

Energy dissipation
Reduce radiated power
More power efficient
Energy efficient protocols and routing algorithms
Better trade-off between communication and local computing

Size
Higher integration (System-on-Chip or SoC)

Cost
Standard Digital CMOS Technology

Evolution of Microelectronics: the SoC Paradigm

Silicon Process Technology
0.13m CMOS
~100 millions of devices, 3 GHz internal Clock

Paradigm Shift in SoC Design

System on a Chip
System on a board

Evolutionary Problems
Emerging new technologies:
Greater complexity
Increased performance
Higher density
Lower power dissipation

Key Challenges
Improve productivity
HW/SW codesign
Integration of analog & RF IPs
Improved DFT

Evolutionary techniques:
- IP (Intellectual Property) based design
- Platform-based design

Migration from ASICs to SoCs

ASICs are logic chips designed by end customers to
perform a specific function for a desired application.
ASIC vendors supply libraries for each technology
they provide. In most cases, these libraries contain
predesigned and preverified logic circuits.
ASIC technologies are:
gate array
full custom

Migration from ASICs to SoCs

In the mid-1990s, ASIC technology evolved from a
chip-set philosophy to an embedded-cores-based
system-on-a-chip concept.
An SoC is an IC designed by stitching
together multiple stand-alone VLSI
designs to provide full functionality for
an application.
An SoC compose of predesigned
models of complex functions known
as cores (terms such as intellectual
property block, virtual components,
and macros) that serve a variety of
applications.

Three forms of SoC design

The scenario for SoC design is characterized by three forms:
1. ASIC vendor design: This refers to the design in which all the
components in the chip are designed as well as fabricated by
an ASIC vendor.
2. Integrated design: This refers to the design by an ASIC vendor
in which all components are not designed by that vendor. It
implies the use of cores obtained from some other source
such as a core/IP vendor or a foundry.
3. Desktop design: This refers to the design by a fabless
company that uses cores which for the most part have been
obtained from other source such as IP companies, EDA
companies, design services companies, or a foundry.

SoC Design Challenges

Why does it take longer to design SOCs compared to
traditional ASICs?
We must examine factors influencing the degree of difficulty and
Turn Around Time (TAT) (the time taken from gate-level netlist to
metal mask-ready stage) for designing ASICs and SOCs.

For an ASIC, the following factors influence TAT:

Frequency of the design

Number of clock domains
Number of gates
Density
Number of blocks and sub-blocks

The key factor that influences TAT for SOCs is system

integration (integrating different silicon IPs on the same IC).

SoCs vs. ASICs

SoC is not just a large ASIC

Architectural approach involving significant design
reuse
Addresses the cost and time-to-market problems

SoC methodology is an incremental step over ASIC

methodology

SoC design is significantly more complexities

IP reuse and Platform-based design increase

productivity, but not enough

Even with extensive IP reuse, many of the ASICs

design problems remain, plus many more ...

From ASICs to SoCs

Technology vs. Productivity vs.

Complexity

System on Chip benefits

Typical approach :

With SoC

Define requirements

Define requirements

Design with off-the shelf chips

Design with off-the shelf cores

- at 0.5 year mark : first prototypes

- 1 year : ship with low margins/loss
start ASIC integration

- at 0.5 year mark : first prototypes

- 1 year : ship with high margin and
market share

- 2 years : ASIC-based prototypes

- 2.5 years : ship, make profits (with
competition)

IpSec

IP cores

mem

CPU

USB
hub

Typical : $70
DSP

Proc

Up to now : collection of chips

mem
CPU

Now : collection of cores

Typical : $10

IpSec

DSP

CoProc

USB
hub

Typical applications of SoC

An SoC is a system on an IC that integrates software and hardware
Intellectual Property (IP) using more than one design methodology for the
purpose of defining the funcionality and behavior of the proposed system.

The designed system

is application specific.

Typical applications of SoC:

microprocessor, media processor,

GPS controllers, cellular phones,
GSM phones, smart pager ASICs,
digital television, video games,
PC-on-a-chip

consumer devicecs,
networking,
communications, and
other segments of the electronics industry.

A common set of problems facing everyone who is

designing complex chips
Time-to-market pressures demand rapid development.
Quality of results (performance, area, power) - key to market success.
Increasing chip complexity makes verification more difficult.
Deep submicron issues make timing closure more difficult.
The development team has different levels and areas of expertise, and
is often scattered throughout the world.
Design team members may have worked on similar designs in the
past, but cannot reuse these designs because the design flow, tools, and
guidelines have changed.
SoC designs include embedded processor cores, and thus a significant
software component, which leads to additional methodology, process,
and organizational challenges.
Reusing macros (called cores, or IP) that have already been
designed and verified helps to address all of the problems above.

Design for Reuse

To be fully reusable, the hardware macro must be:
Designed to solve a general problem easily configurable to fit
different applications.

Designed for use in multiple technologies For soft macros, this

mean that the synthesis scripts must produce satisfactory quality of results with a
variety of libraries. For hard macros, this means having an effective porting strategy
for mapping the macro onto new technologies.

Designed for simulation with a variety of simulators Good

design reuse practices dictate that both a Verilog and VHDL version of each model
and verification testbench should be available, and they should work with all the
major commercial simulators.

Designed with standards-based interfaces Unique or custom

interfaces should be used only if no standards-based interface exists.

Design for Reuse cont.

To be fully reusable, the hardware macro must be:
Verified independently of the chip in which it will be used
Often, macros are designed and only partially tested before being integrated into
a chip for verification. Reusable designs must have full, stand-alone testbenches
and verification suites that afford very high levels of test coverage.

Verified to a high level of confidence This usually means very

rigorous verification as well as building a physical prototype that is tested in an
actual system running real software.

Fully documented in terms of appropriate applications and

restrictions In particular, valid configurations and parameter values must be
documented. Any restrictions on configurations or parameter values must be
clearly stated. Interfacing requirements and restrictions on how the macro can be
used must be documented.

Intellectual Property
Utilizing the predesigned modules
enables:

Resources vs. Number of Uses

to

avoid reinventing the wheel

for every new product,
to

accelerate the development

of new products,
to

assemble various blocks of a

large ASIC/SoC quite rapidly,
to

reduce the possibility of

failure based on design and
verification of a block for the first
time.
These predesigned modules are commonly called
Intellectual Property (IP) cores or Virtual Components
(VC).

What is MPSoC
MPSoC is a system-on-chip that contains multiple
instruction-set processors (CPUs).
The typical MPSoC is a heterogeneous multiprocessor:
there may be several different types of processing elements (PEs),
the memory system may be heterogeneously distributed around
the machine, and the interconnection network between the PEs
and the memory may also be heterogeneous.

MPSoCs often require large amounts of memory. The device may

have embedded memory on-chip as well as relying on off-chip
commodity memory.

The design process of SoCs

SoC designs are made possible by deep submicron technology. This
technology presents a whole set of design challenges including:

interconnect delays,

clock and power distribution, and

the placement and routing of millions of gates.

These physical design problems can have a significant impact on

the functional design of SoCs and on the design process itself.
The first step in system design is specifying the required functionality.
The second step is to transform the system funcionality into an
architecture which define the system implementation by specifying the
number and types of components and connections between them.

Define Hardware-Software Codesign

Hardware-Software Codesign is the concurrent and co-operative
design of hardware and software components of a system.
The SoC design process is a hardware-software codesign in
which design productivity is achived by design reuse.

The design process is the set of design tasks that transform

an abstract specification model into an architectural model.

Design Proces
A canonical or
generic form of
an SoC design
These chips have:
one (several) processors
large amounts of memory
bus-based architectures
peripherals
coprocessors
and I/O channels

Waterfall vs.
Spiral Design Flow
The traditional model for
ASIC development is often
called a waterfall model.
The project transitions
from phase to phase in a
step function, never
returning to the activities
of the previous phase.

Design processes in flow diagrams

The first part of the design process consists of recursively developing,
verifying, and refining a set of specifications until they are detailed
enough to allow RTL coding to begin.
The specifications must completely describe all the interfaces between
the design and its environment, including:

Hardware Functionality; External interfaces to other hardware (pins,

buses, and how to use them); Interface to SW (register definitions); Timing;

Performance; Physical design issues such as area and power

Software Functionality; Timing; Performance; Interface to HW SW

structure, kernel

Type of of specifications:
Formal specifications the desired characteristics of the design are
defined independently of any implementation.
Executable specifications are typically an abstract model for the
hardware and/or software being specified, and currently more useful for
describing functional behavior in most design situations.

ASIC Typical Design Steps

Typical ASIC
design can take
up to two years
to complete

Top Level Design

Unit Block Design
Unit Block Verification
Integration and Synthesis
Trial Netlists

Timing Convergence
& Verification
System Level Verification
Fabrication
DVT Prep
DVT
6

12

12
48
61

14 ??

Time to Mask order

Time in Weeks

SoC Typical Design Steps

With increasing Complexity
of ICs and decreasing
Geometry, IC Vendor steps
of Placement, Layout and
Fabrication are unlikely to
be greatly reduced.

Top Level Design

Unit Block Design
Unit Block Verification
Integration and Synthesis
Trial Netlists
Timing Convergence
& Verification
System Level Verification
Fabrication

In fact there is a greater

risk that Timing
Convergence steps will
involve more iteration.

DVT Prep
DVT
4

14
24

Time in Weeks
Time to Mask order
33

Need to reduce time before

Vendor Steps.
Need to consider Layout
issues up-front.

SoC Typical Design Steps

SoC Architecture already defined.
Flexible to scale in frequency and
complexity.
Allows new IP cores, new technology
to be integrated.

Top Level Design

Unit Block Design
Unit Block Verification
Integration and Synthesis
Trial Netlists
Timing Convergence
& Verification
System Level Verification
Fabrication
DVT Prep

Separate the design of the reusable

IP from the design of the SoC.
Build the SoC from library of tested IP.
Unit design consists only of any
additional core features or wrapping
new IP to enable integration.

DVT
4

14
24

Time in Weeks
Time to Mask order

Reusable IP purchased from external

sources, developed from in-house
designs or designed as separate
project off critical SoC development
path.

Design Methodology
A Back-End Design Flow or Generic Physical Flow.

ASIC Methodology

SOC Methodology

How to Design an SOC

How to Design an SOC

How to Design an SOC

How to Design an SOC

How to Design an SOC

System on Chip - Testing

SOCs are complex designs combining logic, memory and

mixed-signal circuits in a single IC

I/O pads

Main SOC testing challenges

Self-test
control

Memory
array

DSP
core

Legacy
core

Interface
control

IP hard
core

Embedded
DRAM

1149.1 TAP controller

Core level test: Embedded cores are

tested as a part of the system
I/O pads

CPU
core

Test access: Due to absence of physical

access to the core peripheries, electronic
access mechanism required
SOC level test: SOC test is a single
composite test including individual core,
and UDL test and test scheduling

Test data volume for core-based SOC designs is very high.

New techniques are required to reduce testing time, test cost, and
the memory requirements of the automatic test equipment (ATE)

Verification
Today about 70% of design
cost and effort is spent on
verification.
Verification teams are often
almost twice as large as
the RTL designers at
companies developing ICs.
Traditionally, chip design
verification focuses on
simulation.
However, new verification
techniques are emerging.

Design for Integration

A key issue in SOC design is integration of silicon IPs (cores).
Integration of IPs directly affects the complexity of SOC designs and also
influences verification of the SOC.
Verification is faster and easier if the SOC interconnect is simple and
unified (use an on-chip communication system or intelligent on-chip bus).
There is no standard for OCBs; they are chosen almost exclusively by the
specific application for which they will be used and by the designer's preference.

Two main types of OCBs (on-chip bus) and their characteristics

OCB

Speed

Bandwidth

Arbitration

Example

System

High

High

Complex

ARM AHB

Peripheral

Low

Low

Simple

PCI Bus

A Typical Gateway SoC Architecture

An example of typical gateway VoIP (Voice over Internet Protocol)
system-on-a-chip diagram.
A gateway VoIP SoC is a device used for functions such as vocoders,
echo cancellation, data/fax modems, and VoIP protocols.

A Traditional SOC Architecture (bus-based)

In a typical SOC, there
are complex data flows
and multiple cores such
as CPUs, DSPs, DMA,
and peripherals.
Therefore,
resource sharing
becomes an issue,
communication between
IPs becomes very
complicated.

Sonics SiliconBackplane Used in SOC Design Architecture

The CPU, DMA, and the DSP engine all share the same bus (the CPU or
the system bus). Also, there are dedicated data links, a lot of control wires
between blocks, and peripheral buses between subsystems
there is interdependency between blocks and a lot of wires in the chip.
Therefore, verification, test, and physical design all become difficult to fulfill.
A solution to this system integration is to use an intelligent, on-chip
interconnect that unifies all the traffic into a single entity.
An example of this is Sonics SMART Interconnect SiliconBackplane
MicroNetwork.
When compared to a traditional CPU bus, an on-chip interconnect such as
Sonics SiliconBackplane has the following advantages:
Higher efficiency
Flexible configuration
Guaranteed bandwidth and latency
Integrated arbitration

SoC Market Growth

Conclusions
An System on Chip (SoC) is an integrated circuit that implements
most or all of the function of a complete electronic system.

Four vital areas of SoC:

Higher levels of abstraction

IP and platform re-use

IP creation ASIPs,
interconnect and algorithm

Earlier software development

and integration