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    CMOS Logic Gates: Gagandeep Singh

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    Gagandeep Singh Dhingra
    The document discusses CMOS logic gates and sequential circuits. It describes the basic structure of CMOS combinational circuits using pull-up and pull-down networks. It then analyzes the switching threshold of a 2-input CMOS NOR gate and NAND gate. Various CMOS sequential circuits are discussed such as latches, flip-flops, and memory cells. Specific implementations of D latches and a 6T SRAM cell are also covered.

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    CMOS Logic Gates: Gagandeep Singh

    Uploaded by

    Gagandeep Singh Dhingra
    140 views37 pages
    The document discusses CMOS logic gates and sequential circuits. It describes the basic structure of CMOS combinational circuits using pull-up and pull-down networks. It then analyzes the switching threshold of a 2-input CMOS NOR gate and NAND gate. Various CMOS sequential circuits are discussed such as latches, flip-flops, and memory cells. Specific implementations of D latches and a 6T SRAM cell are also covered.

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    CMOS Technology

    Original Title

    CMOS Logic Gates

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    The document discusses CMOS logic gates and sequential circuits. It describes the basic structure of CMOS combinational circuits using pull-up and pull-down networks. It then analyzes the switching threshold of a 2-input CMOS NOR gate and NAND gate. Various CMOS sequential circuits are discussed such as latches, flip-flops, and memory cells. Specific implementations of D latches and a 6T SRAM cell are also covered.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    140 views37 pages

    CMOS Logic Gates: Gagandeep Singh

    Uploaded by

    Gagandeep Singh Dhingra
    The document discusses CMOS logic gates and sequential circuits. It describes the basic structure of CMOS combinational circuits using pull-up and pull-down networks. It then analyzes the switching threshold of a 2-input CMOS NOR gate and NAND gate. Various CMOS sequential circuits are discussed such as latches, flip-flops, and memory cells. Specific implementations of D latches and a 6T SRAM cell are also covered.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 37

    CMOS Logic Gates

    Gagandeep
    Singh,

    CMOS Circuits
    Basic CMOS combinational circuits consists
    of Pull Up (p type) and Pull Down (n type)
    networks.
    Two types of circuits are there: VCombinational CircuitsVV
    V
    Pull
    Sequential Circuits
    UP
    V
    DD

    A
    B
    C
    N

    VA
    VB
    VC
    VN

    VOUT
    Pull
    Down

    CMOS NOR Gate


    Two Input CMOS
    NOR Gate.
    For the Analysis of
    Switching
    threshold point ,we
    assume :VA = VB
    (W/L)p,A=(W/L)p,B
    (W/L)n,A=(W/L)n,B

    Switching Threshold
    Analysis
    By definition the input threshold
    voltage is equal to output threshold
    voltage at switching threshold.
    VA = VB = Vout = Vthreshold
    For NMOS transistors, VGS = VDS,
    therefore they are operating in
    saturation.
    ID = /2[Vthreshold Vtn]2
    Vthreshold = Vtn + (2ID/ ) -------------(1)

    Switching Threshold
    Analysis
    For M4, VSD=VSG, So it is operating in
    Saturation mode.
    Hence
    For M3, VSD < VSG - |VTP|, so it is
    operating in linear region.
    Hence
    Also ID3 = ID4, Hence
    VDD VI |VTP| = 2 (ID/p) -------------(2)

    Switching Threshold
    Analysis
    From (1) and (2), we can have VI for
    NOR gate as :-

    For CMOS Inverter , it is :-

    CMOS NAND Gate


    Two Input CMOS
    NAND Gate.
    For the Analysis of
    Switching
    threshold point ,we
    assume :VA = VB
    (W/L)p,A=(W/L)p,B
    (W/L)n,A=(W/L)n,B

    Switching Threshold
    Analysis
    Both the PMOS would be operating in
    Saturation Region. Why?
    M1 is operating in Saturation Mode.
    M2 is operating in Linear Mode.
    Using the same procedure, we find
    the VI for NAND gate as:-

    Complex CMOS Gates


    Z = A(D+E) +BC and so on.

    CMOS XOR Gate

    CMOS XNOR
    (Equivalence)Gate

    Full Adder Using CMOS


    Factor Sum in terms of Carry_out
    Sum = ABC + (A + B + C)(~Carry_out)

    Full Adder Using CMOS

    Pseudo NMOS Logic Gates


    Replace the Pull
    Down network with
    single PMOS
    (always on).
    Lesser Gates,
    Lesser Area.
    Higher static power
    dissipation
    NAND Gate using Pseudo NMOS Technique

    Sequential Circuits
    The output in sequential circuits is
    determined by the current input and
    previously applied input variables.
    To remember the previously applied
    inputs, sequential circuits have a memory.
    There is a direct or indirect feedback
    between output and input.
    Three types :- Bistable, Monostable and
    Astable

    Sequential Circuits

    Behavior of Bistable
    Elements
    Cross coupled
    inverter shows
    bistable behavior.
    Drain current of 1
    is the gate current
    of 2.
    We know, id= gmvgs
    hence
    ig1 = id2 = gmvg2
    Ig2 = id1 =
    gmvg1.(3)

    Cont

    (4)

    Cont.
    Expressing the gate voltages, in
    terms of gate charges:-

    Solution of the above equation can


    be given as :Where 0 =

    Cont
    From the expression obtained for q in
    the previous slide , similar expression
    can be deduced for V.

    Magnitude of both voltages increases


    with time exponentially, depending
    upon Vo1 and Vo2, V01, Vo2 reaches VOL
    or VOH.

    CMOS SR Latch
    Using NOR Gate

    CMOS SR Latch
    Using NAND Gate

    Clocked SR Latch

    CMOS D Latch

    D Latch Implementation - I

    D Latch Implementation - II

    Schmitt Trigger Circuits


    VTC with hysteresis
    Useful for removing
    noise from output.

    Spice Netlist for Schmitt


    Trigger

    Operation of CMOS Schmitt


    VDD
    Trigger
    M2
    Vin =
    Vx0
    =Vy=5V
    Vz= VDD -VT
    in = VT0n=
    Vin V=3.5V
    M51V
    Linear
    M5
    starts
    M6 Saturation
    turn
    V
    =
    2v on
    Min4to
    ON
    M
    Of0
    Vx4 =
    M5 & M6 Saturation
    Vz= 2.976

    Vy
    M3
    M1
    Vin

    Vx
    M4

    VDD
    M6

    M5

    Vz

    GND

    Vout

    Operation of CMOS Schmitt


    VDD
    Trigger
    Vin = 5V
    Vx= 0
    M4,M5 are ON
    M3 in saturation
    Vy =1.5
    Vin = 4 v
    M1 is about to on
    M23 of,
    Vin =
    v M3
    M1 Saturation
    and M3 in
    saturation
    Vy = 2.02 V
    V = 1.5 v
    M2in of
    Vy = 2.79V
    M2 turned ON
    VX pulled up to
    VDD

    M2
    Vy
    M3
    Vin

    M1
    Vx
    M4

    VDD
    M6

    M5

    vz

    GND

    Vout

    VTC of Schmitt Trigger


    Circuit
    If Input voltage
    increases than
    VM+ , output
    voltage goes to
    VOL.
    If Input voltage
    becomes less than
    VM-, output voltage
    goes to VOH

    Noise suppression Using Schmitt


    Trigger
    V in

    M+

    t0

    out

    t0 + tp

    6T SRAM Cell
    bit
    word

    bit_b

    SRAM Reading a 0
    Word Line

    Bit Line

    Word Line

    Bit Line

    VDD
    VDD
    M3
    M5

    Node
    1 1 Voltage
    Increase in Node
    M1
    Linear Mode

    VDD
    VDD V1

    M4
    Linear Mode
    VDD

    M6

    Node 2
    M2

    VDD

    Reading a 0
    v1max <= Vtn of M2
    Also M5 operates in saturation and
    M1 in Linear mode. Therefore
    (M5/2)[VDD-V1 Vtn]2 = (M1/2)[2(VDDVtn)V1-V12]
    M5/M1= (W/L)5/(W/L)1
    < [2(VDD -1.5Vtn)Vtn] /(VDD -2Vtn)2]

    SRAM Writing a 0
    Word Line

    Word Line

    Bit Line

    Bit Line

    VDD
    VDD
    Linear Mode
    M3
    M5

    VDD

    VDD

    Vdd-V1

    Node
    1 1 Voltage
    decrease in Node
    M1

    M4
    0
    Node 2
    Linear Mode
    M2

    M6

    Writing a 0
    VDD-V1 <= Vtn of M2
    Also M6 operates in saturation and M 2
    and M3 are in Linear mode.
    At VNode1 = Vtn, M5 linear and M3 in
    saturation Mode
    (M3/2)[0 VDD Vtp]2 = (M5/2)[2(VDD-Vtn)VtnVtn2]
    (W/L)3/(W/L)5
    < (n/p)[2(VDD -1.5Vtn)Vtn] /(VDD +2Vtp)2]

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