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Reconfiguration Architectures: by Nagasai.B 108113022

This document discusses different architectures for reconfigurable computing systems. It describes pipeline reconfigurable systems which use physical pipeline stages to implement virtual pipeline stages. It also discusses block reconfigurable systems which are made up of independent reconfigurable blocks that can implement configurations. Finally, it discusses using parallel processing in reconfigurable hardware by statically parallelizing applications into hardware threads that execute on the reconfigurable device.

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62 views14 pages

Reconfiguration Architectures: by Nagasai.B 108113022

This document discusses different architectures for reconfigurable computing systems. It describes pipeline reconfigurable systems which use physical pipeline stages to implement virtual pipeline stages. It also discusses block reconfigurable systems which are made up of independent reconfigurable blocks that can implement configurations. Finally, it discusses using parallel processing in reconfigurable hardware by statically parallelizing applications into hardware threads that execute on the reconfigurable device.

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aarthi100
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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RECONFIGURATION

ARCHITECTURES
By
Nagasai.B
108113022

PIPELINE RECONFIGURABLE
SYSTEMS
Pipeline recongurable arrays use a series of

physical pipeline stages to implement the virtual


pipeline stages of congurations.
A virtual pipeline stage can be relocated to any
physical pipeline stage, and the number of virtual
stages is generally not constrained by the number
of physical stages.
Physical pipeline stage is xed in a recongurable
hardware whereas virtual pipeline stages
correspond to the application being run in the
system and are different for different applications.

Cont.
The most wellknown pipeline recongurable

architecture is PipeRench, which is designed to


implement deeply pipelined congurations,
subdivided into a set of virtual pipeline stages.
At runtime, the virtual pipeline stages are
assigned to physical pipeline stage computation
units. These units are arranged in a unidirectional
ring, as shown in Figure.
Although pipeline stages may be implemented in
different physical locations over time, the virtual
pipeline appears xed to its own pipeline stages,
with each stage receiving input from its
predecessor and generating output to its
successor.

PIPELINE SYSTEM

Cont.
Pipeline reconguration eliminates many of

the difculties of using recongurable


hardware as virtual hardware, but places
restrictions on the circuits that can be
implemented as information can only
propagate forward through the pipeline
stages, and any feedback connections must
be completely contained within a single stage.
The number of virtual pipeline stages of an

application that the hardware can implement


at a run time is restricted by the on-chip
memory, which is the major drawback of
pipeline recongurable systems.

BLOCK RECONFIGURABLE SYSTEMS


Rather than providing one large recongurable fabric,

block recongurable hardware are made up of


multiple discrete blocks that can be used
independently.
Each independent block can contain many logic
resources(or logic blocks). An individual conguration
may occupy one or more blocks, but blocks may not
be subdivided between congurations.
Blocks are connected either through a crossbar
structure or a bus/network, as shown in Figure.
Block recongurable devices have the ability to
relocate congurations to different blocks at runtime
and hence the blocks are called Swappable Logic
Units(SLU).

Cont
A heterogeneous multiprocessor may t the

block recongurable model, provided multiple


blocks of recongurable hardware are present
and congurations can be relocated between
the blocks for computational exibility.
These architectures may contain a single
communication network used by the
congurable blocks and other resources such
as microprocessors and custom circuitry.
The Pleiades recongurable architecture is
one such architecture that has some of these
features (a heterogeneous multiprocessor with
multiple recongurable blocks).

PARALLEL PROCESSING IN
RECONFIGURABLE SYSTEMS
As high performance of computing systems is strongly

required for a high-functionality embedded system, an


ubiquitous, and a high-speed personal computer, we
need to develop and enhance several computing
technologies to satisfy these requirements.
One of solutions is parallel processing. Super-scalar
processors improve a performance, extracting ILP
(Instruction Level Parallelism) from a sequential
program dynamically.In VLIW (Very Long lnstmction
Word) processors, a compiler extracts ILP statically.
Multi-processors execute some parts of a program
parallelized by a compiler or some individual jobs on
many processors.

Cont
Parallel processing in a recongurable

hardware involves parallelizing an application


program statically into threads by traditional
parallelizing methods(Just like in conventional
multiprocessor systems).
They are translated to hardware
threads(eg:stream of bits for FPGA based
recongurable hardware systems), and then,
they are executed by a recongurable
computing system directly.
In a recongurable device, the hardware
threads(eg:FPGAs) cooperate with high-speed
communication and synchronization using
ags and registers.

OVERVIEW OF TARGET SYSTEMS

Cont.
Fig.1 shows a concept of recongurable

computing system we consider. The system


has one or more recongurable parts. Each
recongurable part is connected to a system
interface that mediates between the
recongurable part and a system bus.
The plane consists of the recongurable part

and system interface. A program translated to


the hardware is assigned to a plane and
executed basically. If a program is greater
than the capacity of one plane, the program is
divided to the small protions and they are
executed by several planes.

Cont.
A program written in high level language such

as C is translated to an object data by the


compiler for the target recongurable system
The created object data consists of the circuit
data section(Conguration data)
corresponding to the code section in a
conventional processor, and data section.
The monitor processor loads such object data
into the memory through a memory card, a
disk or network. To reduce bus traffic. the
system can have a dedicated bus and a
memory for conguration data. Then, monitor
processor sends some information to a plane
that is not executing any program via control

Cont
The specied system interface congures the

recongurable part using the circuit data in


memory, and sets the address translation
mechanism with information sent by monitor
processor. This mechanism may have base
registers for generating a linear address and
have a MMU to perform memory protection.

REFERENCES
Recongurable Computing The Theory and Practise of

FPGA-Based Computation, Edited by Scott Hauck and


Andre Dehon.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&
arnumber=1413826 A New Parallel Processing Paradigm
Using A Recon. gurable Computing System.
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&
arnumber=1676350 Task Preloading Schemes for
Recongurable Parallel Processing Systems.
http://ieeexplore.ieee.org/stamp/stamp.jsp?
tp=&arnumber=4275159&tag=1 Recongurable
Parallel Processing System Based on A Modied Ant
Colony Algorithm

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