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Computer System Operation I/O Structure Storage Structure Storage Hierarchy Hardware Protection General System Architecture

This chapter discusses the core components and structures of computer systems including: I/O structure with synchronous and asynchronous operations; storage hierarchy from registers to disk; hardware protection mechanisms like dual mode operation, memory protection using base/limit registers; and network structures for local and wide area networks. The key aspects covered are how I/O devices interface with the CPU using interrupts, how data is transferred through different storage levels using caching, and the hardware support for separating system/user modes and protecting memory.

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Owusu-Agyemang Frank
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© © All Rights Reserved
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63 views

Computer System Operation I/O Structure Storage Structure Storage Hierarchy Hardware Protection General System Architecture

This chapter discusses the core components and structures of computer systems including: I/O structure with synchronous and asynchronous operations; storage hierarchy from registers to disk; hardware protection mechanisms like dual mode operation, memory protection using base/limit registers; and network structures for local and wide area networks. The key aspects covered are how I/O devices interface with the CPU using interrupts, how data is transferred through different storage levels using caching, and the hardware support for separating system/user modes and protecting memory.

Uploaded by

Owusu-Agyemang Frank
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Chapter 2: Computer-System Structures

Computer System Operation


I/O Structure
Storage Structure
Storage Hierarchy
Hardware Protection
General System Architecture

2.1

Silberschatz, Galvin and Gagne 2002

Computer-System Architecture

2.2

Silberschatz, Galvin and Gagne 2002

Computer-System Operation

I/O devices and the CPU can execute concurrently.


Each device controller is in charge of a particular device

type.
Each device controller has a local buffer.
CPU moves data from/to main memory to/from local
buffers
I/O is from the device to local buffer of controller.
Device controller informs CPU that it has finished its
operation by causing an interrupt.

2.3

Silberschatz, Galvin and Gagne 2002

Unix/Linux Kernel interface

2.4
Note: This picture is excerpted from Write a Linux Hardware
Device Driver,
AndrewGalvin
OShauqhnessy,
Unix world
Silberschatz,
and Gagne 2002

Common Functions of Interrupts

Interrupt transfers control to the interrupt service routine

generally, through the interrupt vector, which contains the


addresses of all the service routines.
Interrupt architecture must save the address of the
interrupted instruction.
Incoming interrupts are disabled while another interrupt is
being processed to prevent a lost interrupt.
A trap is a software-generated interrupt caused either by
an error or a user request.
An operating system is interrupt driven.

2.5

Silberschatz, Galvin and Gagne 2002

Interrupt Handling
The operating system preserves the state of the CPU by

storing registers and the program counter.


Determines which type of interrupt has occurred:
polling
vectored interrupt system

Separate segments of code determine what action should

be taken for each type of interrupt

Signal
Value
Action
Comment
------------------------------------------------------------------------SIGHUP
1
Term
Hangup detected on controlling terminal
or death of controlling process
SIGINT
2
Term
Interrupt from keyboard
SIGQUIT
3
Core
Quit from keyboard
SIGILL
4
Core
Illegal Instruction
SIGABRT
6
Core
Abort signal from abort(3)
SIGFPE
8
Core
Floating point exception
SIGKILL
9
Term
Kill signal
SIGSEGV
11
Core
Invalid memory reference
SIGPIPE
13
Term
Broken pipe: write to pipe with no readers
SIGALRM
14
Term
Timer signal from alarm(2)
SIGTERM
15
Term
Termination signal
SIGUSR1
30,10,16
Term
User-defined signal 1
SIGUSR2
31,12,17
Term
User-defined signal 2
:
2.6

Silberschatz, Galvin and Gagne 2002

Interrupt Time Line For a Single Process Doing Output

2.7

Silberschatz, Galvin and Gagne 2002

I/O Structure
After I/O starts, control returns to user program only upon

I/O completion.

Wait instruction idles the CPU until the next interrupt


Wait loop (contention for memory access).
At most one I/O request is outstanding at a time, no

simultaneous I/O processing.

After I/O starts, control returns to user program without

waiting for I/O completion.

System call request to the operating system to allow user

to wait for I/O completion.


Device-status table contains entry for each I/O device
indicating its type, address, and state.
Operating system indexes into I/O device table to determine
device status and to modify table entry to include interrupt.

2.8

Silberschatz, Galvin and Gagne 2002

Two I/O Methods

Synchronous

Asynchronous

2.9

Silberschatz, Galvin and Gagne 2002

Device-Status Table

2.10

Silberschatz, Galvin and Gagne 2002

Direct Memory Access Structure

Used for high-speed I/O devices able to transmit

information at close to memory speeds.


Device controller transfers blocks of data from buffer
storage directly to main memory without CPU
intervention.
Only on interrupt is generated per block, rather than the
one interrupt per byte.

2.11

Silberschatz, Galvin and Gagne 2002

Storage Structure

Main memory only large storage media that the CPU

can access directly.


Secondary storage extension of main memory that
provides large nonvolatile storage capacity.
Magnetic disks rigid metal or glass platters covered with
magnetic recording material
Disk surface is logically divided into tracks, which are

subdivided into sectors.


The disk controller determines the logical interaction
between the device and the computer.

2.12

Silberschatz, Galvin and Gagne 2002

Moving-Head Disk Mechanism

2.13

Silberschatz, Galvin and Gagne 2002

Storage Hierarchy

Storage systems organized in hierarchy.


Speed
Cost
Volatility
Caching copying information into faster storage system;

main memory can be viewed as a last cache for


secondary storage.

2.14

Silberschatz, Galvin and Gagne 2002

Storage-Device Hierarchy

2.15

Silberschatz, Galvin and Gagne 2002

Caching

Use of high-speed memory to hold recently-accessed

data.
Requires a cache management policy.
Caching introduces another level in storage hierarchy.
This requires data that is simultaneously stored in more
than one level to be consistent.

2.16

Silberschatz, Galvin and Gagne 2002

Migration of A From Disk to Register

2.17

Silberschatz, Galvin and Gagne 2002

Hardware Protection

Dual-Mode Operation
I/O Protection
Memory Protection
CPU Protection

2.18

Silberschatz, Galvin and Gagne 2002

Dual-Mode Operation

Sharing system resources requires operating system to

ensure that an incorrect program cannot cause other


programs to execute incorrectly.
Provide hardware support to differentiate between at least
two modes of operations.
1. User mode execution done on behalf of a user.
2. Monitor mode (also kernel mode or system mode)
execution done on behalf of operating system.

2.19

Silberschatz, Galvin and Gagne 2002

Dual-Mode Operation (Cont.)

Mode bit added to computer hardware to indicate the

current mode: monitor (0) or user (1).


When an interrupt or fault occurs hardware switches to
monitor mode.
Interrupt/fault

monitor

user
set user mode

Privileged instructions can be issued only in monitor mode.

2.20

Silberschatz, Galvin and Gagne 2002

I/O Protection

All I/O instructions are privileged instructions.


Must ensure that a user program could never gain control

of the computer in monitor mode (I.e., a user program


that, as part of its execution, stores a new address in the
interrupt vector).

2.21

Silberschatz, Galvin and Gagne 2002

Use of A System Call to Perform I/O

2.22

Silberschatz, Galvin and Gagne 2002

Memory Protection

Must provide memory protection at least for the interrupt

vector and the interrupt service routines.


In order to have memory protection, add two registers that
determine the range of legal addresses a program may
access:
Base register holds the smallest legal physical memory

address.
Limit register contains the size of the range

Memory outside the defined range is protected.

2.23

Silberschatz, Galvin and Gagne 2002

Use of A Base and Limit Register

2.24

Silberschatz, Galvin and Gagne 2002

Hardware Address Protection

2.25

Silberschatz, Galvin and Gagne 2002

Hardware Protection

When executing in monitor mode, the operating system

has unrestricted access to both monitor and users


memory.
The load instructions for the base and limit registers are
privileged instructions.

2.26

Silberschatz, Galvin and Gagne 2002

CPU Protection

Timer interrupts computer after specified period to

ensure operating system maintains control.


Timer is decremented every clock tick.

When timer reaches the value 0, an interrupt occurs.

Timer commonly used to implement time sharing.


Time also used to compute the current time.
Load-timer is a privileged instruction.

2.27

Silberschatz, Galvin and Gagne 2002

Network Structure

Local Area Networks (LAN)


Wide Area Networks (WAN)

2.28

Silberschatz, Galvin and Gagne 2002

Local Area Network Structure

2.29

Silberschatz, Galvin and Gagne 2002

Wide Area Network Structure

2.30

Silberschatz, Galvin and Gagne 2002

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