Digital Integrated Circuits: A Design Perspective
Digital Integrated Circuits: A Design Perspective
A Design Perspective
Jan M. Rabaey
Outline (approximate)
Introduction and Motivation
The VLSI Design Process
Details of the MOS Transistor
Device Fabrication
Design Rules
CMOS circuits
VLSI Structures
System Timing
Real Circuits and Performance
Introduction to VLSI Design
Introduction
The Babbage
Difference Engine
(1832)
25,000 parts
cost: 17,470
Digital Integrated Circuits
Introduction
Introduction
Evolution in Complexity
Introduction
Introduction
CMOS:Complementary MOS
Means we are using both N-channel and Pchannel type enhancement mode Field Effect
Transistors (FETs).
Field Effect- NO current from the controlling
electrode into the output
Introduction
N-Channel Enhancement
mode MOS FET
FourTerminalDevicesubstratebias
TheselfalignedgatekeytoCMOS
Introduction to VLSI Design
Introduction
Introduction
Introduction
Introduction
Scale Example
Consider a chip size of 20mm X 20mm
Consider a transistor size of 2um X
2um
Introduction
Introduction
VLSI Design
But the real issue is that VLSI is about designing
systems on chips.
The designs are complex, and we need to use
structured design techniques and sophisticated
design tools to manage the complexity of the
design.
We also accept the fact that any technology we
learn the details of will be out of date soon.
We are trying to develop and use techniques that
will transcend the technology, but still respect it.
Introduction
Introduction
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
Introduction
D
n+
Tools
Logic design
Electronic/circuit
design
Device physics
Artwork
Applications - system
design
Architectures
Editors
Simulators
Libraries
Module Synthesis
Place/Route
Chip Assemblers
Silicon Compilers
Experts
Introduction
Scalable Designs
Layout techniques also change slowly.
Introduction
Design Approaches
Custom
Gate Array
Introduction
Introduction
Evolution in Speed/Performance
Introduction
Technologies
Bipolar (BJT)
TTL, Schottky
ECL
I^2 L
Introduction
Silicon in 2010
Density AccessTime
(Gbits/cm2)
(ns)
Die Area:
2.5x2.5 cm
DRAM
8.5
10
Voltage:
0.6 V
2.5
10
Technology: 0.07 m DRAM (Logic)
SRAM (Cache)
0.3
1.5
Density
Max. Ave. Power Clock Rate
(Mgates/cm2)
(W/cm2)
(GHz)
Custom
25
54
3
Std. Cell
10
27
1.5
GateArray
5
18
1
Single-Mask GA
2.5
12.5
0.7
FPGA
0.4
4.5
0.25
Digital Integrated Circuits
Introduction
Introduction
8
inch
Introduction
18 inch
Steven P. Levitan 1998
Introduction
Introduction
Introduction
Introduction