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8155 I/O + Timer 8155 I/O + Timer 8255 I/O 8255 I/O 8253/54 Timer 8253/54 Timer

This document provides an overview of serial communication and the 8251 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) controller chip. It describes the differences between serial and parallel communication, synchronous and asynchronous transmission, and simplex and duplex transmission. Error checking methods like parity and cyclic redundancy checks are also covered. The document then explains how the 8251 USART controller works to handle serial input/output in hardware, converting parallel data to serial and vice versa to interface with a microprocessor. Program flows for transmitting and receiving data serially in software and hardware are presented.

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Kamalan Hayanesh
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84 views24 pages

8155 I/O + Timer 8155 I/O + Timer 8255 I/O 8255 I/O 8253/54 Timer 8253/54 Timer

This document provides an overview of serial communication and the 8251 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) controller chip. It describes the differences between serial and parallel communication, synchronous and asynchronous transmission, and simplex and duplex transmission. Error checking methods like parity and cyclic redundancy checks are also covered. The document then explains how the 8251 USART controller works to handle serial input/output in hardware, converting parallel data to serial and vice versa to interface with a microprocessor. Program flows for transmitting and receiving data serially in software and hardware are presented.

Uploaded by

Kamalan Hayanesh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Hierarchy of I/O Control

Devices
2 Port
8155
I/O +
Timer

8253/54
Timer

8259
Interrupt
controller

6 mode
timer

8237
DMA
controller

(A,B),
No
Bidirection
al
HS mode
2 Port (A,B)
8255(C)
4 mode
A is
I/O timer Bidirectional
HS mode (C)
Extra controls

8251
Serial I/O
USART
controller

Outline
Parallel Vs Serial Communication
Characteristics of serial
communication
Synchronous/A-synchronous,
Simplex/Duplex, Baud rate and Error
Correction

Introduction to 8251 USART


controller

Data Comm: Serial Vs


Parallel
Data

Serial

Transmissio
n

Cheaper
Slower

Parallel
Parallel

Faster
Data skew
Limited to small distances
Synchronou
s

Serial

ASynchronou
s

Serial Communication:
How ?
Two basic modes of data transmission
Parallel to
Serial to
serial
parallel
Conversion
Conversion
1
1
1
1
0
0
0 10010011 0 Receiv
Sender
1
1 er
0
0
0
0
1
1
Serial
Transmission

1
1
0
0
Sender
1
0
0
1
Parallel
Transmission

1
1
0
0 Receiv
1 er
0
0
1

Type of Serial
Communication
Synchronous
Sender and receiver must synchronize
Done in hardware using phase locked loops
(PLLs)

Block of data can be sent


More efficient : Less overhead than
asynchronous transmission
Expensive

Asynchronous
Each byte is encoded for transmission
Start and stop bits

No need for sender and receiver


synchronization

Type of Serial Communication


Transmission Gaps

Sender

Data

Data

Data

Receiver

Asynchronous transmission
CL
K
Sender

Data

Data

Data

Data

Data

Synchronous transmission

Receiver

Framing in
Asynchronous
Character oriented
Each character carried start bit and
stop bits
When No data are being transmitted
Receiver stay at logic 1 called mark, logic
0 is Space

Framing:
Transmission begins with one start bit
(low/0)
Followed by DATA (8bit) and

Type of Serial Communication


1
start
bit

Asynchronous transmission1 or 2 Stop


bit

Source data

1
1
LSB

0
1

0
MSB

Start
Bit

Time
8 bit Data

Start
Bits

Simplex and Duplex


Transmission
Simplex
Data are transmitted in one directions
Example: CPU to printer

Duplex
Data flow in both direction
Half Duplex (Transmission goes on way
at a time)
Full Duplex (Both ways simultaneously)

Rate of transmission
Rate at which bits are transmitted
(BAUD)
Number of signal changes per
second
Bit time: how long the Bit stay On or
Of
Printer, Terminal Baud Adjustable
(50-9600)
1200Baud means: Bit stay for
1/1200=0.83ms

Error Check
Parity Check
Even parity: When odd numbers of 1 make D7=1
Send Even number of 1

Odd parity: When even number of 1 make D7=1


Send Odd number of 1

Check Sum
Used for block of data
Sum of all Bytes without carry and 2s complements
Total Sum Result should be Zero

Cyclic Redundancy Code (CRC)


Synchronous Communication
Stream of Data can be represented by Cyclic
polynomial that divided by a constant polynomial
Reminder to set Bits and Send out as check for error

Steps to be followed :
Transmitting
Inform RX the start bit, end bits and parity
check
Convert parallel word into stream of bits
Create a transmit word by adding start,
end and proper parity bit .
Transmit one bit at a time with appropriate
time delay using one data line
Time delay is determined by the speed of
transmission

Steps to be followed :
Receiving
Recognize bit of transmission
Receive serial bits, one bit at a time
Dismantle the start bits, end bit,
parity bit, Data bits
Check the error and recognize the
end of transmission
Convert serial data bit in to parallel
word

Software control Asynchronous I/0


using Microprocessor

8 bit Data to be send


Steps:
Output a start bit
Convert the character to be sent in a
stream of serial bits with appropriate
delay
Add a parity information if needed
Output one or two stop bit

Serial Transmission in
Software
8
0
8
5

D
D
7
D
6
D
5
D
4
D
3
D
2
D
1
0

Decode
WRb

CS
b

Output
Port

Program/Flow chat to Transmit


data serially
Output Bit using D0
Start
Set up Character bit
counter
Send start bit
Wait bit time
Get Char in ACC

Wait bit time


Rotate
Rotate Next bit in D0
Decrement the bit
counter
Is
Las
t
bit
?
Add parity if
necessary
Send two stop bit
Retur
n

Serial Reception in
Software
8
0
8
5

D
D
7
D
6
D
5
D
4
D
3
D
2
D
1
0

DRb

Decode

Input
Port
CS
b

Flow chart to receive


data serially
Start
Read out put port
NO

Is it
bit
Start?

Wait half bit time


NO

Is bit
Still
low ?

Set up Bit counter


Clear register to
Save bits
Wait bit time
Read input port
Save bit
Get ready to next bit
Decrement bit
counter
Is
Las
t
bit
?
Check parity if
necessary
Wait for two stop bit
Retur
n

8085 Serial I/O lines


Serial Input Data (SID)
Serial Output Data (SOD)
Instruction SIM is necessary to output
data
Interpretations
(ACC
D7 D6
D D4 contents)
D D D D0
SO
D

SDE (0/1
Dis/Ena SOD)

For interrupts

MVI A, 80 ; Set D7 in the ACC=1


RAR
;Set D6 =1 and bring carry
into D7
SIM
; output D7

Data transmission Program on SOD

Transmit an ASCII Char stored in Register B


MVI
MVI
XRA
NXTbit:
RAR
SIM
CALL
STC
MOV
RAR

B ASCIIDatabyte ; get data byte in B


C,0BH
; set up counter for 11 bits
A
; reset carry to 0
MVI
A,80H
;set D7=1 in ACC
;bring Carry in D7 and set D6=1
;output D7
DELAYBittime ;wait for fixed time (BWT)
;set Carry 1
A,B
;Place ASIII car in acc
; place ASCII D0 in Carry
;and shift 1 in D7
MOV B,A
;Save B
DCR
C
JNZNXTbit
RET

Hardware control Serial


I/O
Programmable chip 8251
Requirement of HW control serial I/O
An input/output port are required for
interfacing
Converts data bits in to Parallel to serial
& vice versa
Data transfer to be synchronized
between I/O
USART (Universal Synchronous
Asynchronous Receiver and
Transmitter )

UART/USART
Writing a program compatible with all
diferent serial communication protocols is
difficult and it is an inefficient use of
microprocessor.
UART: Universal Asynchronous
Receiver/Transmitter chip.
USART: Universal
Synchronous/Asynchronous
Receiver/Transmitter chip.
The microprocessor sends/receives the
data to the UART in parallel, while with I/O,
the UART transmits/receive data serially.
8251 functions are integrated into

UART / CPU interface

CPU

status
(8 bit)
xmit/
8251
rcv
data
(8 bit)

serial
port

UART/USART
8251 USART
8250/16450 UART is a newer version of 8251.
16550 is the latest version UART.

Thanks

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