Operating System and Computer Architecture

CT049-3-1

CPU and Memory

Degree Level 1

Prepared by: Abubakar S. Santruraki First Prepared on: 10-4-13 Last Modified on: 10-4-13
Quality checked by: Team
Copyright 2013 Asia Pacific University of Information Technology

CPU: Major Components

ALU (arithmetic logic unit)
Performs calculations and comparisons

CU (control unit)
Performs fetch/execute cycle
Accesses program instructions and issues commands to the ALU
Moves data to and from CPU registers and other hardware
components

Subcomponents:
Memory management unit: supervises fetching instructions and
data from memory
I/O Interface: sometimes combined with memory management
unit as Bus Interface Unit

CT049-3-1 Operating System and Computer Architecture

CPU and Memory

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System Block Diagram

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The Little Man Computer

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Concept of Registers
Small, permanent storage locations within the CPU
used for a particular purpose
Manipulated directly by the Control Unit
Wired for specific function
Size in bits or bytes (not in MB like memory)
Can hold data, an address or an instruction

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Registers
Use of Registers
Scratchpad for currently executing program
Holds data needed quickly or frequently

Stores information about status of CPU and currently executing

program
Address of next program instruction
Signals from external devices

General Purpose Registers

User-visible registers
Hold intermediate results or data values, e.g., loop counters
Equivalent to LMCs calculator
Typically several dozen in current CPUs

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Special-Purpose Registers
Program Count Register (PC)
Also called instruction pointer

Instruction Register (IR)

Stores instruction fetched from memory

Memory Address Register (MAR)

Memory Data Register (MDR)
Status Registers
Status of CPU and currently executing program
Flags (one bit Boolean variable) to track condition like
arithmetic carry and overflow, power failure, internal
computer error

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Register Operations
Stores values from other locations (registers
and memory)
Addition and subtraction
Shift or rotate data
Test contents for conditions such as zero or
positive

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CPU and Memory

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Operation of Memory
Each memory location has a unique address
Address from an instruction is copied to the MAR
which finds the location in memory
CPU determines if it is a store or retrieval
Transfer takes place between the MDR and
memory
MDR is a two way register

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Relationship between MAR,

MDR and Memory
Data

Addres
s

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MAR-MDR Example

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Visual Analogy of Memory

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Individual Memory Cell

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Memory Capacity
Determined by two factors
1. Number of bits in the MAR
LMC = 100 (00 to 99)
2K where K = width of the register in bits

2. Size of the address portion of the instruction

4 bits allows 16 locations
8 bits allows 256 locations
32 bits allows 4,294,967,296 or 4 GB

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RAM: Random Access Memory

DRAM (Dynamic RAM)
Most common, cheap, less electrical power, less heat,
smaller space
Volatile: must be refreshed (recharged with power) 1000s
of times each second

SRAM (static RAM)

Faster and more expensive than DRAM
Volatile
Small amounts are often used in cache memory for highspeed memory access

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Nonvolatile Memory
ROM
Read-only Memory
Holds software that is not expected to change over the life
of the system

EEPROM
Electrically Erasable Programmable ROM

Flash Memory

Faster than disks but more expensive

Uses hot carrier injection to store bits of data
Slow rewrite time compared to RAM
Useful for nonvolatile portable computer storage

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Fetch-Execute Cycle
Two-cycle process because both instructions
and data are in memory
Fetch
Decode or find instruction, load from memory into
register and signal ALU

Execute
Performs operation that instruction requires
Move/transform data

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LMC vs. CPU

Fetch and Execute Cycle

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Load Fetch/Execute Cycle

1. PC MAR

Transfer the address from the

PC to the MAR

2. MDR IR

Transfer the instruction to the

IR

3. IR[address] MAR

Address portion of the

instruction loaded in MAR

4. MDR A

Actual data copied into the

accumulator

5. PC + 1 PC

Program Counter incremented

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Store Fetch/Execute Cycle

1. PC MAR

Transfer the address from the

PC to the MAR

2. MDR IR

Transfer the instruction to the

IR

3. IR[address] MAR

Address portion of the

instruction loaded in MAR

4. A MDR*

Accumulator copies data into

MDR

5. PC + 1 PC

Program Counter incremented

*Notice how Step #4 differs for LOAD and STORE

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ADD Fetch/Execute Cycle

1. PC MAR

Transfer the address from the

PC to the MAR

2. MDR IR

Transfer the instruction to the

IR

3. IR[address] MAR

Address portion of the

instruction loaded in MAR

4. A + MDR A

Contents of MDR added to

contents of accumulator

5. PC + 1 PC

Program Counter incremented

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LMC Fetch/Execute
SUBTRACT

IN

OUT

HALT

PC MAR

PC MAR

PC MAR

PC MAR

MDR IR

MDR IR

MDR IR

MDR IR

IR[addr] MAR

IOR A

A IOR

A MDR A

PC + 1 PC

PC + 1 PC

PC + 1 PC
BRANCH

BRANCH on Condition

PC MAR

PC MAR

MDR IR

MDR IR

IR[addr] PC

If condition false: PC + 1 PC
If condition true: IR[addr] PC

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Bus
The physical connection that makes it possible
to transfer data from one location in the
computer system to another
Group of electrical or optical conductors for
carrying signals from one location to another
Wires or conductors printed on a circuit board
Line: each conductor in the bus

4 kinds of signals
1. Data
2. Addressing
3. Control signals
4. Power (sometimes)
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Bus Characteristics

Number of separate conductors

Data width in bits carried simultaneously
Addressing capacity
Lines on the bus are for a single type of signal or
shared
Throughput - data transfer rate in bits per second
Distance between two endpoints
Number and type of attachments supported
Type of control required
Defined purpose
Features and capabilities

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Bus Categorizations
Parallel vs. serial buses
Direction of transmission
Simplex unidirectional
Half duplex bidirectional, one direction at a time
Full duplex bidirectional simultaneously

Method of interconnection
Point-to-point single source to single destination
Cables point-to-point buses that connect to an external device

Multipoint bus also broadcast bus or multidrop bus

Connect multiple points to one another

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Parallel vs. Serial Buses

Parallel
High throughput because all bits of a word are transmitted
simultaneously
Expensive and require a lot of space
Subject to radio-generated electrical interference which
limits their speed and length
Generally used for short distances such as CPU buses and
on computer motherboards

Serial
1 bit transmitted at a timed
Single data line pair and a few control lines
For many applications, throughput is higher than for parallel
because of the lack of electrical interference
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Point-to-point vs. Multipoint

Plugin
device

Broadcas
t bus
Example:
Ethernet

Shared among
multiple devices
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Classification of Instructions
Data Movement (load, store)
Most common, greatest flexibility
Involve memory and registers
Whats this size of a word ? 16? 32? 64 bits?

Arithmetic
Operators + - / * ^
Integers and floating point

Boolean Logic
Often includes at least AND, XOR, and NOT

Single operand manipulation instructions

Negating, decrementing, incrementing, set to 0

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More Instruction Classifications

Bit manipulation instructions
Flags to test for conditions

Shift and rotate

Program control
Stack instructions
Multiple data instructions
I/O and machine control

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Register Shifts and Rotates

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Program Control Instructions

Program control
Jump and branch
Subroutine call
and return

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Stack Instructions
Stack instructions
LIFO method for organizing information
Items removed in the reverse order from that in which they
are added

Push
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Pop
CPU and Memory

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Block of Memory as a Stack

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Multiple Data Instructions

Perform a single operation on multiple pieces of data
simultaneously
SIMD: Single Instruction, Multiple Data
Commonly used in multimedia, vector and array processing
applications

CT049-3-1 Operating System and Computer Architecture

CPU and Memory

Thursday, August 27, 2015

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Multiple Data Instructions

OPCODE: task
Source OPERAND(s)
Result OPERAND

Addresses

Location of data (register, memory)

Explicit: included in instruction
Implicit: default assumed
OPCODE

CT049-3-1 Operating System and Computer Architecture

Source

Result

OPERAND

OPERAND

CPU and Memory

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Instruction Format
Machine-specific template that specifies
Length of the op code
Number of operands
Length of operands
Simple
32-bit
Instruction
Format

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Instructions
Instruction
Direction given to a computer
Causes electrical or optical signals to be sent through specific circuits
for processing

Instruction set
Design defines functions performed by the processor
Differentiates computer architecture by the

Number of instructions
Complexity of operations performed by individual instructions
Data types supported
Format (layout, fixed vs. variable length)
Use of registers
Addressing (size, modes)

CT049-3-1 Operating System and Computer Architecture

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Instruction Word Size

Fixed vs. variable size
Pipelining has mostly eliminated variable instruction size
architectures

Most current architectures use 32-bit or 64-bit words

Addressing Modes
Direct
Mode used by the LMC

Register Deferred
Also immediate, indirect, indexed

CT049-3-1 Operating System and Computer Architecture

CPU and Memory

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Instruction Format Examples

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END

Q&A
CT049-3-1 Operating System and Computer Architecture

CPU and Memory

Thursday, August 27, 2015

09:19:25 AM