0% found this document useful (0 votes)
58 views13 pages

CS370 - Spring 2003 Hazards/Glitches

This document discusses timing behavior in combinational networks and how to avoid hazards and glitches. It covers gate delays, pulse shaping circuits, types of hazards like static and dynamic hazards. Solutions proposed are adding redundant terms to cover all adjacent transitions, designing hazard-free networks where all adjacent ones are covered by a term, and avoiding asynchronous inputs. An example of a glitch is shown and how to eliminate it by expressing the function in a hazard-free form.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
58 views13 pages

CS370 - Spring 2003 Hazards/Glitches

This document discusses timing behavior in combinational networks and how to avoid hazards and glitches. It covers gate delays, pulse shaping circuits, types of hazards like static and dynamic hazards. Solutions proposed are adding redundant terms to cover all adjacent transitions, designing hazard-free networks where all adjacent ones are covered by a term, and avoiding asynchronous inputs. An example of a glitch is shown and how to eliminate it by expressing the function in a hazard-free form.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 13

CS370 Spring 2003

Hazards/Glitches

Chapter Overview
Time Response in Combinational Networks
Gate Delays and Timing Waveforms
Hazards/Glitches and How To Avoid Them

Time Response in Combinational Networks


Timing behavior of circuits is emphasized
waveforms are useful to visualize what is happening
Logic simulation can be used to create these waveforms
Hazards : momentary change of signals at the outputs
can be useful -- pulse shaping circuits
can be a problem -- glitches: incorrect circuit operation

Terms:
gate delay -- time for change at input to cause change at output.
rise time -- time for output to transition from low to high voltage
fall time -- time for output to transition from high to low voltage

Time Response in Combinational Networks


Pulse Shaping Circuit

A' A = 0

3 gate delays
D remains high for
three gate delays after
A changes from low to high

F is not always 0!

Time Response in Combinational Networks


Another Pulse Shaping Circuit

+
Resistor
A
Open
Switch

Close Switch
Initially undefined

Open Switch

B
D

Time Response in Combinational Networks


Hazards/Glitches and How to Avoid Them
Unwanted switching at the outputs
Occur because delay paths through the circuit experience
different propagation delays
Danger if logic "makes a decision" while output is unstable
OR hazard output controls an asynchronous input (these
respond immediately to changes rather than waiting for a
synchronizing signal called a clock)
Solutions:
wait until signals are stable (by using a clock)
never use circuits with asynchronous inputs
design hazard-free circuits (single-bit changes in the inputs)

Time Response in Combinational Networks


Hazards/Glitches and How to Avoid Them
1

1
Static
1-hazard

Input change causes output to go from 1 to 0 to 1

Static
0 0-hazard

Input change causes output to go from 0 to 1 to 0

0
1
0
1

Dynamic
1 hazards
0

Kinds of Hazards

Input change causes a double change


from 0 to 1 to 0 to 1 OR
from 1 to 0 to 1 to 0

Time Response in Combinational Circuits


Glitch Example

A
\C
\A
D

G1

1
0

G2

A
\C

1
G3

\A
D

G1

1
0

1
G3

G2

01

\A
D

1
0
1

G1

G3
G2

A
\C

ABCD = 1101

F
\A
D

0
G1
1
0
1

10

11

10

0
G3

G2

11

F = A' D + A C'

input change within product term


1

01

ABCD = 1101

ABCD = 1100

A
\C

AB
00
CD
00 0

A
\C
F
\A
D

ABCD = 0101 (A is still 0)

input change that spans product terms


output changes from 1 to 0 to 1

0
G1
1
1

0
G3

G2

ABCD = 0101 (A is 1)

Time Response in Combinational Networks


Glitch Example
General Strategy: add redundant terms
F = A' D + A C' becomes A' D + A C' + C' D
This eliminates 1-hazard? How about 0-hazard?
AB
00
CD
00 0

Re-express F in PoS form:


F = (A' + C')(A + D)

01

A
01

11

10

1
D

Glitch present!
Add term: (C' + D)
This expression is equivalent
to the hazard-free SoP form of F

11

10

Time Response in Combinational Networks


Glitch Example
Start with expression that is free of static 1-hazards
F = A C' + A' D + C' D
Work with complement:
F' = (A C' + A' D + C' D)'
= (A' + C) (A + D') (C + D')
= A C + A C D' + C D' + A' C D' + A' D'
= A C + C D' + A' D'
covers all the adjacent 0's in the K-map
free of static-1 and static-0 hazards!

Time Response in Combinational Networks


Static hazards
Solution:
Add redundant terms to insure all adjacent
transitions are covered by terms
F2 = A C' + A' D + C' D + A B + B D

100
A
B
C
D
F
F2
1's hazards in F
corrected in F2

Time Response in Combinational Networks


Designing Networks for Hazard-free operation

AB
00
CD
00 0
01

A
01

11

10

Simply place transient output function in a form


that guarantees that all adjacent ones are
covered by a term
no term of the transient output function contains
both a variable and its complement
D

11

F(A,B,C,D) = m(1,3,5,7,8,9,12,13,14,15)

10

F = A B + A' D + B D + A C' + C' D

= (A' + B + C') D + A (B + C')


(factored by distributive law, which does not
introduce hazards since it does not depend on
the complementarity laws for its validity)

Time Response in Combinational Networks


Dynamic Hazards
Example with Dynamic \A 1
Hazard
B

01

\B 1 0
\C
1

G1

01

Slow
G2

G3

1 01

10
A 0
\B
10

G5
G4

10

V ery slow

Three different paths from B or B' to output


ABC = 000, F = 1 to ABC = 010, F = 0
different delays along the paths:
G1 slow, G4 very slow
Handling dynamic hazards very complex
Beyond our scope

1 01 0
F

You might also like