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    Cache Memory

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    hariprasathk
    Cache memory provides fast access to recently used data and instructions by storing copies of frequently accessed main memory locations. There are three main types of cache organization: direct mapped, fully associative, and set associative. Direct mapped cache has a fixed mapping between blocks of main memory and cache lines. Fully associative cache allows a memory block to be placed in any cache line. Set associative cache divides the cache into sets, and a memory block can be placed in any line within a set. Modern processors use hierarchical cache designs with multiple levels such as L1, L2, and L3 caches to improve performance.

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    Cache Memory

    Uploaded by

    hariprasathk
    89 views39 pages
    Cache memory provides fast access to recently used data and instructions by storing copies of frequently accessed main memory locations. There are three main types of cache organization: direct mapped, fully associative, and set associative. Direct mapped cache has a fixed mapping between blocks of main memory and cache lines. Fully associative cache allows a memory block to be placed in any cache line. Set associative cache divides the cache into sets, and a memory block can be placed in any line within a set. Modern processors use hierarchical cache designs with multiple levels such as L1, L2, and L3 caches to improve performance.

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    operating system, cache memory, features of cache memory

    Original Title

    cache memory

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    Cache memory provides fast access to recently used data and instructions by storing copies of frequently accessed main memory locations. There are three main types of cache organization: direct mapped, fully associative, and set associative. Direct mapped cache has a fixed mapping between blocks of main memory and cache lines. Fully associative cache allows a memory block to be placed in any cache line. Set associative cache divides the cache into sets, and a memory block can be placed in any line within a set. Modern processors use hierarchical cache designs with multiple levels such as L1, L2, and L3 caches to improve performance.

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    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    89 views39 pages

    Cache Memory

    Uploaded by

    hariprasathk
    Cache memory provides fast access to recently used data and instructions by storing copies of frequently accessed main memory locations. There are three main types of cache organization: direct mapped, fully associative, and set associative. Direct mapped cache has a fixed mapping between blocks of main memory and cache lines. Fully associative cache allows a memory block to be placed in any cache line. Set associative cache divides the cache into sets, and a memory block can be placed in any line within a set. Modern processors use hierarchical cache designs with multiple levels such as L1, L2, and L3 caches to improve performance.

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    Download as ppt, pdf, or txt
    of 39

    Cache memory

    Direct Cache Memory

    Associate Cache Memory

    Set Associative Cache Memory

    How can one get fast memory with less expense?


    It is possible to build a computer which uses only
    static RAM (large capacity of fast memory)
    This would be a very fast computer
    But, this would be very costly

    It also can be built using a small fast memory for


    present reads and writes.
    Add a Cache memory

    Locality of Reference Principle


    During the course of the execution of a program,
    memory references tend to cluster
    - e.g. programs - loops, nesting,
    data
    strings, lists, arrays,

    This can be exploited with a Cache memory

    Cache Memory Organization


    Cache - Small amount of fast memory
    Sits between normal main memory and CPU
    May be located on CPU chip or in system
    Objective is to make slower memory system look like fast memory.

    There may be more levels of cache (L1, L2,..)

    Cache Operation Overview


    CPU requests contents of memory location
    Cache is checked for this data
    If present, get from cache (fast)
    If not present, read required block from main memory to cache
    Then deliver from cache to CPU
    Cache includes tags to identify which block(s) of main memory
    are in the cache

    Cache Read Operation - Flowchart

    Cache Design Parameters


    Size of Cache
    Size of Blocks in Cache
    Mapping Function how to assign blocks
    Write Policy - Replacement Algorithm when blocks
    need to be replaced

    Size Does Matter

    Cost
    More cache is expensive

    Speed
    More cache is faster (up to a point)
    Checking cache for data takes time

    Typical Cache Organization

    Cache/Main Direct Caching Memory


    Structure

    Direct Mapping Cache Organization

    Direct Mapping Summary


    Each block of main memory maps to only one cache
    line
    i.e. if a block is in cache, it must be in one specific place

    Address is in two parts


    - Least Significant w bits identify unique word
    - Most Significant s bits specify which one memory block

    All but the LSBs are split into


    a cache line field r and
    a tag of s-r (most significant)

    Example Direct Mapping Function


    16MBytes main memory
    i.e. memory address is 24 bits
    - (224=16M) bytes of memory

    Cache of 64k bytes


    i.e. cache is 16k
    - (214) lines of 4 bytes each

    Cache block of 4 bytes


    i.e. block is 4 bytes
    - (22) bytes of data per block

    Example Direct Mapping Address Structure


    Tag s-r

    Line or Slot r
    14

    24 bit address

    2 bit word identifier (4 byte block)


    likely it would be wider

    22 bit block identifier


    8 bit tag (=22-14)
    14 bit slot or line

    No two blocks sharing the same line have the same Tag field

    Check contents of cache by finding line and checking Tag

    Word w
    2

    Illustration
    of Example

    Direct Mapping pros & cons


    Pros:
    Simple
    Inexpensive
    ?

    Cons:
    One fixed location for given block
    If a program accesses 2 blocks that map to
    the same line repeatedly, cache misses are
    very high thrashing & counterproductivity
    ?

    Associative Cache Mapping


    A main memory block can load into any line of cache
    The Memory Address is interpreted as tag and word
    The Tag uniquely identifies block of memory
    Every lines tag is examined for a match
    Cache searching gets expensive/complex or slow

    Fully Associative Cache Organization

    Associative Caching Example

    Comparison of Associate to Direct Caching


    Direct Cache Example:
    8 bit tag
    14 bit Line
    2 bit word
    Associate Cache Example:
    22 bit tag
    2 bit word

    Set Associative Mapping


    Cache is divided into a number of sets
    Each set contains a number of lines
    A given block maps to any line in a given set
    e.g. Block B can be in any line of set i

    e.g. with 2 lines per set


    We have 2 way associative mapping
    A given block can be in one of 2 lines in only
    one set

    Two Way Set Associative Cache Organization

    2 Way Set Assoc Example

    Comparison of Direct, Assoc, Set Assoc Caching


    Direct Cache Example (16K Lines):
    8 bit tag
    14 bit line
    2 bit word
    Associate Cache Example (16K Lines):
    22 bit tag
    2 bit word
    Set Associate Cache Example (16K Lines):
    9 bit tag
    13 bit line
    2 bit word

    Replacement Algorithms (1)


    Direct mapping
    No choice
    Each block only maps to one line
    Replace that line

    Replacement Algorithms (2)


    Associative & Set Associative
    Likely Hardware implemented algorithm (for speed)
    First in first out (FIFO) ?
    replace block that has been in cache longest

    Least frequently used (LFU) ?


    replace block which has had fewest hits

    Random ?

    Write Policy Challenges


    Must not overwrite a cache block unless main memory
    is correct
    Multiple CPUs/Processes may have the block cached
    I/O may address main memory directly ?
    (may not allow I/O buffers to be cached)

    Write through
    All writes go to main memory as well as cache
    (Typically 15% or less of memory references are
    writes)

    Challenges:
    Multiple CPUs MUST monitor main memory traffic to
    keep local (to CPU) cache up to date
    Lots of traffic may cause bottlenecks
    Potentially slows down writes

    Write back
    Updates initially made in cache only
    (Update bit for cache slot is set when update occurs
    Other caches must be updated)
    If block is to be replaced, memory overwritten only if
    update bit is set
    ( 15% or less of memory references are writes )
    I/O must access main memory through cache or
    update cache

    Coherency with Multiple Caches


    Bus Watching with write through
    1) mark a block as invalid when another
    cache writes back that block, or
    2) update cache block in parallel with
    memory write
    Hardware transparency
    (all caches are updated simultaneously)
    I/O must access main memory through cache or update cache(s)
    Multiple Processors & I/O only access non-cacheable memory
    blocks

    Choosing Line (block) size


    8 to 64 bytes is typically an optimal block
    (obviously depends upon the program)
    Larger blocks decrease number of blocks in a given cache size,
    while including words that are more or less likely to be accessed
    soon.
    Alternative is to sometimes replace lines with adjacent blocks
    when a line is loaded into cache.
    Alternative could be to have program loader decide the cache
    strategy for a particular program.

    Multi-level Cache Systems


    As logic density increases, it has become advantages and
    practical to create multi-level caches:
    1) on chip
    2) off chip

    L2 cache may not use system bus to make caching faster


    If L2 can potentially be moved into the chip, even if it
    doesnt use the system bus
    Contemporary designs are now incorporating an on
    chip(s) L3 cache . . . .

    Split Cache Systems


    Split cache into:
    1) Data cache
    2) Program cache
    Advantage:
    Likely increased hit rates
    - data and program accesses display different behavior
    Disadvantage:
    Complexity

    Intel Caches
    80386 no on chip cache
    80486 8k using 16 byte lines and four way set associative organization
    Pentium (all versions) two on chip L1 caches
    Data & instructions

    Pentium 3 L3 cache added off chip


    Pentium 4
    L1 caches

    8k bytes
    64 byte lines
    four way set associative

    L2 cache

    Feeding both L1 caches


    256k
    128 byte lines
    8 way set associative

    L3 cache on chip

    Pentium 4 Block Diagram

    Intel Cache Evolution


    Problem

    Solution

    Processoronwhichfeature
    firstappears

    Externalmemoryslowerthanthesystembus.

    Addexternalcacheusingfaster
    memorytechnology.

    386

    Increasedprocessorspeedresultsinexternalbusbecoming
    abottleneckforcacheaccess.

    Moveexternalcacheonchip,
    operatingatthesamespeedasthe
    processor.

    486

    Internalcacheisrathersmall,duetolimitedspaceonchip

    AddexternalL2cacheusingfaster
    technologythanmainmemory

    486

    Createseparatedataandinstruction
    caches.

    Pentium

    Createseparatebacksidebusthatruns
    athigherspeedthanthemain(front
    side)externalbus.TheBSBis
    dedicatedtotheL2cache.

    PentiumPro

    MoveL2cacheontotheprocessor
    chip.

    PentiumII

    AddexternalL3cache.

    PentiumIII

    MoveL3cacheonchip.

    Pentium4

    ContentionoccurswhenboththeInstructionPrefetcher
    andtheExecutionUnitsimultaneouslyrequireaccessto
    thecache.Inthatcase,thePrefetcherisstalledwhilethe
    ExecutionUnitsdataaccesstakesplace.

    Increasedprocessorspeedresultsinexternalbusbecoming
    abottleneckforL2cacheaccess.

    Someapplicationsdealwithmassivedatabasesandmust
    haverapidaccesstolargeamountsofdata.Theonchip
    cachesaretoosmall.

    PowerPC Cache Organization (Apple-IBM-Motorola)

    601 single 32kb 8 way set associative


    603 16kb (2 x 8kb) two way set associative
    604 32kb
    620 64kb
    G3 & G4
    64kb L1 cache
    8 way set associative

    256k, 512k or 1M L2 cache


    two way set associative

    G5
    32kB instruction cache
    64kB data cache

    PowerPC G5 Block Diagram

    Comparison of Cache Sizes


    Processor

    Type

    YearofIntroduction

    Primarycache(L1)

    2ndlevelCache(L2)

    3rdlevelCache(L3)

    IBM360/85

    Mainframe

    1968

    16to32KB

    PDP11/70

    Minicomputer

    1975

    1KB

    VAX11/780

    Minicomputer

    1978

    16KB

    IBM3033

    Mainframe

    1978

    64KB

    IBM3090

    Mainframe

    1985

    128to256KB

    Intel80486

    PC

    1989

    8KB

    Pentium

    PC

    1993

    8KB/8KB

    256to512KB

    PowerPC601

    PC

    1993

    32KB

    PowerPC620

    PC

    1996

    32KB/32KB

    PowerPCG4

    PC/server

    1999

    32KB/32KB

    256KBto1MB

    2MB

    IBMS/390G4

    Mainframe

    1997

    32KB

    256KB

    2MB

    IBMS/390G6

    Mainframe

    1999

    256KB

    8MB

    Pentium4

    PC/server
    Highendserver/
    supercomputer
    Supercomputer

    2000

    8KB/8KB

    256KB

    2000

    64KB/32KB

    8MB

    2000

    8KB

    2MB

    PC/server

    2001

    16KB/16KB

    96KB

    4MB

    SGIOrigin2001

    Highendserver

    2001

    32KB/32KB

    4MB

    Itanium2

    PC/server

    2002

    32KB

    256KB

    6MB

    IBMPOWER5

    Highendserver

    2003

    64KB

    1.9MB

    36MB

    CRAYXD1

    Supercomputer

    2004

    64KB/64KB

    1MB

    IBMSP
    CRAYMTAb
    Itanium

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