Lecture-7

MOS SPICE Models

Dr. Arti Noor,

M. Tech Division, CDAC Noida.
Email : [email protected]

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What is SPICE?

• SPICE is simulation tool for circuits.

• Picking of correct SPICE level / model can

save simulation / design time.

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What is modeling?

• Future prediction.
In this case you are trying to design an IC to meet a
certain specification.

• Many Models to evaluate same thing why?

– The more accurate/complex the model the more time

it takes to get your answer.

– Can use the fastest / less accurate model first to get a

rough idea of the “solution space” of interest.
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SPICE modeling

• SPICE stands for Simulation Program with Integrated

Circuit Emphasis.

• Developed at Berkeley.

• Latest version is BSIM4.

• Hspice is Avanti’s version.
• Spectre is Cadence’s version for UNIX.
• OrCAD is for the PC.
• PSPICE is the spice algorithm for the PC.
But here we use Tanner TSPICE in the lab.
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SPICE modeling (contd.)

• SPICE does analog simulations of a digital

circuits.

• The are four process corners FF, SS, FS,

and SF.

• We will use extracted parameters from real

process lines.

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SPICE Levels

• Level 1
– Square-law current voltage.
• Level 2
– Detailed analytical model.
• Level 3
– Semi empirical model.
• BSIM4
– sub-micron

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Transient SPICE Model

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SPICE Levels
Level 1

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SPICE Levels
Level 1

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SPICE Levels
Level 1

kT  ni 
2φF = 2 ln 
 

q N
 A

Thus level 1 is characterize by Five parameters

k , VTo , γ , 2φF , λ

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Level-2 Model
This model has the following features :

• Does not use GCA.

• Calculates threshold voltage.
• Takes variations of mobility with electric field.
• Variation of channel length.
• Saturation of carrier velocity.
• Sub threshold conduction.
• Level two harder to do by hand.

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Level-2 Model
• To calculate current, bulk depletion charges are taken into account. Current
equation is solved using voltage dependent Bulk charge term:

( V
VGS −VFB − 2 φF − DS
2 ) VDS 
−2γ 3/ 2 
k W

 3 [( ]
ID =
(1−λVDS ) L 3/ 2
VDS −VBS + 2 φF ) −( −VBS + 2 φF )
• The equation shows current variation with λ,Y, VBS. The saturation voltage
is calculated as

( 2
VDsat =VGS −VFB − 2 φF +γ 2 1− 1+ (

1
γ2
VGS −VFB ) )
I D = I Dsat
( 1−λVDS )

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Level-2 Model
• Mobility variations: surface mobility deceases with increasing VG. Mobility
variation is taken into account as

U
  e
ε tocU c 
k ( new ) = k  si 
 (
 εox Vgs −VT −U tVds ) 

• Uc is gate to channel critical field, Ut is gate to channel critical field variation
due to drain voltage. Ue is exponential fitting parameter. The channel length
modulation parameter is defined as

∆L =
2 εSi
qN A
[ VDS −VDsat
4
+ 1+ (
VDS −VDsat
4 )
2
]
∆L
λ = L V
eff DS

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Level-2 Model
• Velocity saturation parameter : the inversion layer charge for Vds =Vdsat is

I Dsat
Q = W .v
inv max

∆L = X D ( X D . vmax
2µ ) 2
+VDS −VDsat

2 εsi
X =
D qN A N eff

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Level-3 Model

• semi-empirical model.

• Uses simpler expressions than MOS2

plus empirical equations to fit experimental
data.

• Improves accuracy and reduces

simulation time.

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Level-3 Model
• Level 3 is for short channel MOSFET . The majority of equations at this
level are empirical. The aim is to improve the accuracy by reducing
complexity and calculation time. Current equation can be written as

W  1 +F 
I = µ .C . V −V − BV .V
D s ox L  gs T 2 ds  ds
eff  
γ.F
F = s +F
B n
4. 2φ +V
F SB
• FB shows bulk charge dependence, Fs and μS are influenced by short-
channel effects, Fn includes narrow width effects.

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Level-3 Model
• The surface mobility dependence on gate voltage is defined as

µ =
µ
s
1 +.
V

gs
ϕ V 
−
t 

µ
µ
eff
=
V
s
1+ .
s v
µ
ds
.L
m
ax eff

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Comparison of Models

• Level 1 is not very accurate. It is useful for hand

calculation and rough estimation of circuit
performance.

• Level 2 is analytic model and supports various

second order effect. It is very complex model and
takes maximum CPU time.

• Level 3 is semi-empirical model. It has same

accuracy as level 2. takes less CPU time. It has many
flitting parameters to calculate.
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Next Topic

MOS Inverter : Static Characteristics

(Chapter-5)

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