8086 Microprocessor

Its a 40 pin IC (Integrated circuit)

It has 20 address lines, so it can address 1 Mb
memory locations
8086 has 16 data line which is multiplexed with
address line (AD0 to AD15)
So it is 16 bit MP
It can be operated in two modes
1. Maximum mode
2. Minimum mode

8086 INTERNAL ARCHITECTURE

Divided into two units

1 BIU - Bus interface unit
It fetch the instruction and data from the memory.
2 EU -Execution unit
It get the instruction and data from BIU and executes it.

1024 Byte = 1 kbyte

1024 Kbyte= 1 Mbyte
Each segment contain 64 Kyte
So 1 Mbyte can be split into 16 segments

Bus Interfacing Unit(BIU)

It supply the address to perform read and write operation with

the memory
It fetch the instruction and data from the memory and store
it ,in the instruction queue
From the instruction queue , it will be supplied to the
Execution Unit
BIU contain four segment register each 16 bit width
1. Code segment Register, Data segment Register, Stack
segment Register
Extra Segment Register and One Instruction pointer
With in 1 Mbyte of memory MP can use four segments at a
time.
Size of each segment is 64 Kbyte
The Segment register contain the starting address of the
respective segments

MEMORY ORGANIZATION
By using 20 address line 8086 can access 1 Mbyte memory
8086 can access four segment at a time
1 Code segment contain program 0000
0
2 Data segment contain data
2000
Code
0
3 Stack segment contain stack data
Seg
2FFF
4 Extra segment contain intermediate
F
400
result
00
Data
Each Segment have 64 Kbyte locations
Seg
Base address is given by respective
4FFFF
segment register
60000
Stack
Seg

Extra
Seg
FFFF
F

6FFFF
80000
8FFFF

Address generation
MP need to generate 20 bit address to access memory
if code segment = 2000
And Instruction Pointer = 0050
Then 20 bit address is generated as
Code seg X 16 (H) = 20000 - - Base address
IP
=
0050 - - Effective address
(Base add + Eff add) 20050 - - Physical address
Instruction is fetched from the location 20050

Total 1 Mbyte is divided into two blocks Odd block and Even block
Size of Even block is 512 Kbytes
It contain the locations with even address only
It is enabled by the address line A0
Data bus D0 to D7 is connected with even bank
Size of Odd block is 512 Kbytes
It contain the locations with odd address only
It is enabled by
signal
Data bus D8 to D15 is connected with odd bank
Address line A1 to A19 is connected with both the bank

00001(H) First loc

00003( Second
H)
loc

First loc
Second loc

ODD Bank
512 Kb

Even Bank
512 Kb

C
S

C
S

BHE

D15

A1---

D0 D7

00000(
00002(
H)
H)

 To read 8 bit data any one of the bank is selected by BHE or

A0 line and the address line A1 to A15 select the any one
location in the selected memory bank
If the even bank is selected data is read/ write through D0
to D7,
If the odd bank is selected data is read/ write through D8 to
D15,
Due to this arrangement 16 bit data can by read or write
simultaneously
00001(H First loc
Firstis
loc
00000(
To read 16 bit data both the bank
selected
simultaneously
)00003(H)Second
00002(
Second
locD15 H)
andloc
data is read/write through
D0 to
H)

ODD Bank
512 Kb

Even Bank
512 Kb

C
S

C
S

BHE

D15

A1---

D0 D7

00001(
H)
00003(
H)

First loc
Second
loc

First loc
Second loc

Upper Bank
(ODD Bank)
512 Kb

Lower
Bank
(Even
Bank)
C
512 Kb
S

C
S
BHE

D15
D8
A19

00000(
H)
00002(
H)

A1--A19

A
0

D0 D7

A
0
0000

00000- 0000 0000 0000

0000 BHE=1 ,A0=0 , first
loc Even bank
00001- 0000 0000 0000 0000 0001 BHE=0,A0=1 , first
loc Odd bank
00002- 0000 0000 0000 0000 0010 BHE=1 ,A0=0

The Instruction Queue:

The BIU can fetches and store up to 6 instruction bytes.

The BIU stores these bytes in first-in-first-out register set called
a queue.
When the EU is ready for its next instruction it simply reads the
instruction
byte(s) from the queue in the BIU.
This is much faster then fetching single instruction and
executing, then fetching
the next instruction
Fetching the next instruction while the current instruction
executes is called
pipelining

Execution
Unit
It get the instruction and data from bus interfacing unit(BIU) and
executes it.
It contains
1. Registers
2. Arithmetic and Logic unit
3. Control Unit
1.Registers
(I)General
Purpose registers
AX - the

Accumulator
BX - the Base
Register
- the used
Count
CX
Normally
for storing temporary results
Register
Each of the registers is 16 bits wide (AX, BX, CX, DX)
DX - the Data
Can be accessed as either 16 ( as AX,BX,CX,DX)or 8 bits (as
Register

AL,AH,BL,BH,CL,CH,DL,DH)
Each register have some special purpose
AX
Accumulator
Must be used in Multiplication and Division operations
Must be used in Input and Output operation

 BX

CX

DX

Called as Base register

Used as address register
Called as Counter register
Used as a loop counter
Used in shift and rotate operation
Called as Data register
Used in Multiplication and Division
Used in input and output operation

(II) Pointer and Index register

SP Stack Pointer
BP Base Pointer
SI Source Index
DI Destination Index
All are 16 bit registers cant be used as 8 bit
registers
SP Stack pointer- Supply the address to access the
stack memory
BP base pointer- supply the address to access the
memory

Flag
Register
It is 16 bit register
But only 9 bits are used
Types
1. Conditional Flag
2. Control Flag

Overflow

Carry

Direction

Parity

Interrupt enable

Auxiliary Carry

Trap Zero

6 are conditional flag

Sign
3 are control flag

Conditional fag
It reflect the condition of result of the previous operation
Carry flag
It will be set when the carry is generated in the previous operation like
addition
While performing Subtraction it will act as the borrow flag
Parity Flag
It will set when the result contain even no of ones
Auxiliary Carry Flag
It will be set when the carry is generated from the bit D3 to D4 ,while
performing the
arithmetic operation
Zero Flag
It will be set when the result of the previous operation is zero
Sign Flag
It will be copy of the MSB of the result
Over Flow flag
It will be set when the carry is generated from Bit D14 to D15
It is useful when the signed number system is used
Control flag
Control flags are set or reset deliberately to control the operations of the
execution unit.
Trap Flag (TF):
It is used for single step control.

Interrupt Flag (IF):

It is an interrupt enable/disable flag.
If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is
disabled.
It can be set by executing instruction STI and can be cleared by executing
CLI instruction.
Direction Flag (DF):
It is used in string operation.
If it is set, string bytes are accessed from higher memory address to lower
memory address.
When it is reset, the string bytes are accessed from lower memory address
to higher memory
address.

Control Unit , Arithmetic and Logical Unit

The execution unit (EU) of the 8086 tells the BIU from where to fetch
instructions or Data.
It decodes instructions and executes instruction.
A decoder in the EU translates instructions into a series of actions which is
carried by EU
The EU is has a 16-bit ALU which can add, subtract, AND, OR, XOR,
increment, decrement, complement or shift binary numbers.
The EU contains control circuitry which directs internal operations.

External memory Interface

The data stored in 8086 memory can be 8 bit or 16 bit
To make 8086 to read/write the 8 bit or 16 bit data, memory is
divided into banks
1 Lower bank having even address like 00000,00002,00004 ..
2. Upper bank having odd address like 00001,00003,00005
Size of Lower block is 512 Kbytes
It is enabled by the address line A0
Data bus D0 to D7 is connected with even bank
Size of Upper block is 512 Kbytes
It contain the locations with odd address only
It is enabled by signal
Data bus D8 to D15 is connected with odd bank
Address line A1 to A19 is connected with both the bank

Some Important Companion chips

1. Clock generator 8284
2. Bidirectional Bus Transceiver 8286/8287
3. 8 Bit Input/output Port 8282/8283
4. Bus controller 8288
Clock generator 8284
Functions of the clock generator

1. It generates the clock and supply to 8086

2. It generate the RESET signal, synchronized with clock signal, to
reset 8086
3. It generate READ signal used for wait state logic
4. Pin configuration

- (Input) External crystal is connected between this pin

Crystal frequency must be three times greater than required clock
frequency
EF1 - (Input) Alternate clock input
F/ - (Input) Clock source selection
If it is high clock at EF1 is taken
If it is low clock from crystal connected at X1 and X2 is taken
CLK
-(Out put) It supply the clock to MP
It directly connected to 8086 MP
OSC
- (out Put) Oscillator output running at crystal or EF1 frequency
PCLK -(O/P) It is TTL level signal output for support circuits
CSYNC - (I/P) it is used for clock synchronization
When it is high it stops the clock supply
When it become low it restart the clock supply

MINIMUM MODE SIGNALS

Memory Interface in minimum mode

AL
AD0- E
AD15
A16-A19

8086

LATC
H

BHE
W
R
D
D8-

8286
D15
TRANSCEIV
ER

DT/
R
DEN

MIN/M
X

D0-D7

VC
C

A1A19
A
0

R W CS
D R
Odd
Bank
512
Kb

RD W CS
Even
R
Bank
512
Kb

8282

STB

ALE

STB
8282

STB
8282

8286

8086

8286

REA
DY
RESE
T

CL
K

RDY1

RESE
T

READY

8284

X1

X2

PCLK

 When the pin no 33 (MN/MX) is connected

to VCC 8086 will work in Minimum mode
Address/data bus:
Address bus is 20 bit long (A0-A19), so 1
Mb memory can be connected
Address line A0-A15 are used to connect
I/O devices
It has 16 data lines (D0- D15)
These data lines are multiplexed with the
address lines A0-A15
Address lines A16-A19 are multiplexed
with status lines S3-S6

Status signal
8086 generate four status signals
S3 and S4 indicate which of the segment is
used
S S Segment3
0
0
1
1

4
0
1
0
1

Register
ES
SS
CS
DS

S5 shows the status of internal interrupt

enable flag
S6=0 always

Control signals
BHE/S7 - BUS HIGH ENABLE/STATUS
BHE signal is multiplexed with Status signal S7
BHE signal is used to enable the Odd address bank
S7 become low in interrupt acknowledgement
cycle

Address latch enable (ALE)

it is used to demultiplex the address/data bus
It is used to enable the latch 8282.

M/IO (memory/Io)
it tells whether a memory or I/O transfer is
talking place.
Logic 1 signals a memory operation and logic
0
signals an I/O operation.

DT/R (data transmit/receive)

It signals the direction of data transfer over the bus.
Logic 1 indicates that the bus is in the transmit mode
Logic 0 signals that the bus is in the receive mode
It is connected with direction selection pin of 8286
WR (write)
It signal the write operation with memory or I/O

RD(Read):

It signal the write operation with memory or I/O

-DATA ENABLE:
it is used to enable the transceiver 8286.
DEN is low during each memory and I/O
access.

READY

It is used to interface slower devices

The READY signal can be used to insert
wait states
READY signal in synchronization with clock
is generated by the 8284 based on input at

 Interrupt Signals:
(INTR) Interrupt request
Used by an external device to get the MP
attention
Sampled during the last clock of each instruction
A subroutine address is available in interrupt
vector table

 INTA Interrupt Acknowledgement

When the MPU recognizes an interrupt
request, it send acknowledgement
(INTA) signal.
NMI -nonmaskable interrupt
It is interrupt request line
It has highest priority and cannot be
masked by software

RESET:
Used to reset the MP
MP immediately terminate its present activity.
This signal is generated by 8284, when the
manual reset switch is closed
DMA Interface Signals:
HOLD
It is send by the DMA controller to request
address and data bus control
HLDA
When the MP relive the control of the busses , it
send HLDA signal to DMA controller

 TEST:
This input is examined by the ``Wait'' instruction.
If the TEST input is LOW execution continues,
otherwise the processor waits in an Idle state.

MAXIMUM MODE SIGNALS

 In maximum mode 8086 MP produces

signals for multiprocessor and coprocessor environment
It produce status signals S0,S1,S2.
By using these status signal, Bus
controller produce all the control signals

The signals generated by bus

controller 8288

INTAsignal
IORCsignal
IOWC, AIOWCsignal

Interrupt Acknowledgement
used as I/O Read control
used as I/O Write control

LOCK
Used in multiprocessor system
Used to lockout other processor from using common bus
The LOCK signal is activated by the ``LOCK'' prefix
instruction
QS0,QS1- Queue status
It specifies what operation is performed in Instruction queue

RQ/GT0 RQ/GT1 : Request/ Grant signal

Used for DMA accesses
Each signal is bidirectional ,
Receive the request signal and send the
Acknowledgement
signal through the same pin
RQ/GT0 have highest priority

AL
E