COE 405

Digital System Design Based

on Data Path and Control Unit
Partitioning

Dr. Aiman H. El-Maleh

Computer Engineering Department
King Fahd University of Petroleum & Minerals

Outline

Data Path & Control Unit Partitioning

Traffic Light Controller Design

Algorithmic State Machine (ASM) Chart

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Digital Systems

Digital systems

Control-dominated systems :

being reactive systems responding to external events, such

as traffic controllers, elevator controllers, etc
Data-dominated systems :
requiring high throughput data computation and transport
such as telecommunications and signal processing

Sequential machines are commonly partitioned into

data path units and control units

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Data Path & Control Unit Partitioning

A common design practice decomposes the system in

two parts:

A Data Path (DP): a collection of interconnected modules that

perform all the relevant computation on the data: it can use

both combinational and sequential components
A Control Unit (CU) that coordinates the behavior of the Data
Path by issuing appropriate control signals that guarantee the
correct sequence of operations: it is typically designed as a
single or cooperating FSMs

DP and CU communicate through 2 types of signals:

Control signals are output of the CU to the DP and correctly

synchronize the operations

Condition signals (or flags) are sent from the DP to the CU to
indicate certain data dependent conditions (that could
influence future behavior)

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Data Path & Control Unit Partitioning

Both DP and CU might receive the systems inputs

(Primary inputs) and generate its outputs (Primary
outputs).

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Data Path & Control Unit Partitioning

The general structure of a digital system that performs

a specific task(s) is as follows:

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Data Path & Control Unit Partitioning

External Control Signals: Specify the task required from the

whole circuit (e.g. calculate the average of some integers)

External Status Signals: Indicate the status of the whole

circuit (e.g. finished processing, error or overflow ...etc.)

External Data Inputs/Outputs: Data going into the circuit or

out of it (e.g. the integers to be averaged and their average)

DP Control Signals: Signals generated by the CU to control

different blocks in the DP (e.g. Shift Registers, Counters,
MUXs ...etc.)

DP Status Signals: Signals that indicate the status of some

blocks in the DP (e.g. when a counter reaches 7 or when an
adder produces a carry or an overflow, or when the sign bit
of the result is negative ...etc.)
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Data Path Design

The data path contains blocks that only deal with data;
they do not provide control to any other blocks and
need to be controlled (by the CU).

Data Path blocks can be viewed as the workers that

perform certain tasks (on the data) who need to be
managed by someone (in this case the CU is the
manager that tells every worker in the Data Path what
to do).

Examples of Data Path blocks:

Registers, Counters, Multiplexors, Decoders, Logic Circuits

(AND, OR, etc)

Arithmetic Circuits:

Adders, Subtractors, Comparators, Multipliers, Square root, etc.

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Registers

Parallel load registers to read data in parallel

Load is a synchronous control to control reading the data.

When LOAD is inactive, the register keeps the data as is

Used when we want to read data as fast as possible (in one

clock cycle)

Implemented using D-FFs and MUXs

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Shift Registers

Shift Registers to read data

serially one bit at a time

Shift is a synchronous control

of shifting (register keeps data
as is when Shift is not active)

Digit serial registers that read

data serially one digit at a time,
where the digit size could be
anything (e.g. 4-bits, 8-bits, 16bits etc.) multiple of shift
registers in parallel

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Modulo N (i.e. divide by N) Counters

N counting states: 0, 1, 2, , (N-1)

The following techniques use an n-bit (2n >= N) binary

counter with synchronous clear or parallel load:

Detect terminal count (N 1) and use to synchronously Clear

the counter to 0 (first count) on next clock pulse

Detect terminal count (N 1) to synchronously Load in the
value 0 (first count) on next clock pulse

Modulo 7 (0,1,,6):

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Three-State Devices

Bus isolation with three-state devices

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A Register Bank with a 4-bit Data Bus

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Design Steps

Identify all inputs and outputs for the whole circuit.

Identify, separately, data inputs/outputs and control
inputs/outputs (external status).

Identify the required Data Path blocks and their control

signals and design them.

Identify the input and output signals to the Data Path

and Control unit.

Design the control Unit (start by obtaining the state

diagram, then the next state and output equations and
finally the logic implementation) and connect it to the
DP.

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Example: Traffic Light Controller

Design a digital system that controls the traffic lights

at an intersection:

It receives inputs from all four corners indicating pedestrians

that want to cross

In absence of crossing requests it should allow each direction
30 seconds of green light, followed by 5 seconds of yellow
light and other 30 seconds of red light
In presence of crossing requests at or after 15 seconds,
immediately proceed with yellow
It is assumed that the clock period of the system is 1KHz

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Example: Traffic Light Controller

Is it possible to design the system as a single

combinational circuit or an FSM?

Because of the time delay, a combinational circuit will

not work (we need to make sure that we waited 30
seconds, and then 5 seconds etc.)

However, a sequential circuit is perfectly capable to

deal with the problem

So why bother designing a more complex circuit?

Lets look better at the specification

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Example: Traffic Light Controller

If we were to design the system as a single FSM, we

will have to include in it all the possible conditions.

In particular, we will have to deal with the time delays

by introducing delay states

How many? With a 1KHz clock, we need 1000 clock cycles to

measure one second, 30,000 to measure 30 seconds.

So, we will need more than 30,000 states!
The FSM design will be boring to say the least.

How can we handle the state explosion problem?

We could use counters to measure the time intervals,

and a control unit to coordinate their behavior and deal
with the PI
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Example: Traffic Light Controller

DP/CU for the TLC:

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Example: Traffic Light Controller

DP design: we need to be able to count:

30 seconds (30,000 clock cycles) for the regular green

15 seconds (15,000 clock cycles) for the reduced green
5 seconds (5,000 clock cycles) for the yellow light

Typical counters have:

A reset/clear input: that sets the count to 0

A count enable input: if 1 it allows the counter to increment
A multiple bit count output: reports the current state of the

count
A single bit terminal count: indicates that a total number of
clock cycles are elapsed and the counter is back to 0

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Example: Traffic Light Controller

In order to be able to count 30,000, we need a power

of 2 of at least 32,768 (=215).

30000=(111010100110000)2. If the counter output bits

are 111010100110000 the terminal count is 1

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Example: Traffic Light Controller

Requests reduce the time to 15 seconds, but if 15

seconds have already elapsed you should know it

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Example: Traffic Light Controller

We can have three separate blocks in the DP (for the 30

sec, >=15 sec and 5 sec):

DP composed of 3 16-bit counters, and a bunch of AND and

NOT gates

However, we can do better:

If you look at the specification, the intervals of 5, 15 or 30

seconds are either used in separate times (5 is only used

during the yellow phase) or they can use the same starting
point (the 30 and 15 they actually have to use the same
starting point)
Use just one counter, with three circuits for 5, 30 and >=15
sec.

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Example: Traffic Light Controller

Now, we have a complete DP. Its interface with the CU:

One counter reset input

One FF reset input
Three outputs (TC_30, TC_5, GE_15)
In this case, DP does not use PI nor produces PO (but it is
just a special case)

CU design

Once the DP is finished, the CU design can proceed, as in a

usual FSM design

In this case, the CU has to:

Provide regular switching between green, yellow and red lights

Observe the request inputs and use them in combination with
GE_15 to shorten green lights
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Example: Traffic Light Controller

Possible Moore machine implementation

EN1=TC_30 + GE_15.cross1
EN2=TC_30 + GE_15.cross2
EN3=TC_5

CU outputs (if not shown =0):

State GR: G1=1, R2=1
State T1: Y1=1, R2=1

CNT_RES=1
State YR: Y1=1, R2=1
State T2: R1=1, G2=1
CNT_RES=1, FF_RES=1
State RG: R1=1, G2=1
State T3: R1=1, Y2=1
CNT_RES=1
State RY: R1=1, Y2=1
State T4: G1=1, R2=1
CNT_RES=1, FF_RES=1

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Example: Traffic Light Controller

One more issue to verify:

Are we actually keeping the lights 5, 15 or 30 seconds?

The counters act exactly, but the entire system has a certain

delay that we need to take into account:

The counters start counting only the clock cycle after the
reset (in this case, when the CU enters the states RG, GR
YR and RY)
When they are done counting, the state changes the
following clock tick, and the outputs with them - MOORE
machine
In conclusion, the lights stay on for 1 more clock cycle: we
need to take that into account by reducing the terminal count
to 29,999, 4,999 and 14,999
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Example: Traffic Light Controller

Communication between DP and CU: timing issues

If both DP and CU, as in this example, are clocked, their

interaction has a non-zero delay

A command issued by the CU will be executed only at the
following tick
A condition code issued by the DP will be read and used only
at the following tick (unless the CU is Mealy).
There is potentially a 2-tick delay in the whole interaction

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Algorithmic State Machine (ASM)

Chart

Algorithmic State Machine (ASM) Chart is a high-level

flowchart-like notation to specify the hardware
algorithms in digital systems.

Major differences from flowcharts are:

uses 3 types of boxes: state box (similar to operation box),

decision box and conditional box

contains exact (or precise) timing information; flowcharts
impose a relative timing order for the operations.

From the ASM chart it is possible to obtain

the control
the architecture (data processor)

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Components of ASM Charts

The state box is rectangular in shape. It has at most

one entry point and one exit point and is used to
specify one or more operations which could be
simultaneously completed in one clock cycle.

state

binary
code

one or more
operations

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Components of ASM Charts

The decision box is diamond in shape. It has one entry

point but multiple exit points and is used to specify a
number of alternative paths that can be followed.

deciding
factors

deciding
factors

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Components of ASM Charts

The conditional box is represented by a rectangle with

rounded corners. It always follows a decision box and
contains one or more conditional operations that are
only invoked when the path containing the conditional
box is selected by the decision box.

conditional
operations

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ASM Charts: An Example

A is a register;

Ai stands for ith bit of

the A register.
A = A4A3A2A1

E and F are singlebit flip-flops.

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Register Operations
Registers are present in the data processor for storing
and processing data. Flip-flops (1-bit registers) and
memories (set of registers) are also considered as
registers.

The register operations are specified in either the state

and/or conditional boxes, and are written in the form:
destination register function(other registers)
where the LHS contains a destination register (or part of one)
and the RHS is some function over one or more of the
available registers.

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Register Operations
Examples of register operations:
AB
A0
A A 1

Transfer contents of register B into

register A.
Clear register A.
Decrement register A by 1.

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Timing in ASM Charts

Precise timing is implicitly present in ASM charts.
Each state box, together with its immediately following
decision and conditional boxes, occurs within one
clock cycle.

A group of boxes which occur within a single clock

cycle is called an ASM block.

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Timing in ASM Charts

T0
Initial state
0

S
1

T1

A 0
F 0

A A+1
0

3 ASM blocks

A2

E 0

E 1
0

A3
T2

1
F 1

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Timing in ASM Charts

Operations of ASM can be illustrated through a timing
diagram.

Two factors which must be considered are

operations in an ASM block occur at the same time in one

clock cycle
decision boxes are dependent on the status of the previous
clock cycle (that is, they do not depend on operations of
current block)

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Timing in ASM Charts

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Timing in ASM Charts

T0
Initial state
0

S
1

T1

A 0
F 0

Operations

A A+1
0

A A+1
A A+1
E 0
E 1
A A+1
A A+1
E 0
E 1

A2

E 0

E 1
0

A3
T2

1
F 1

A = A4A3A2A1

A 0
F 0

A A+1
F 1
E 0
A A+1
A A+1
E 0
E 1

Operations

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ASM Chart => Digital System

ASM chart describes a digital system. From ASM
chart, we may obtain:

Controller logic (via State Table/Diagram)

Architecture/Data Processor

Design of controller is determined from the decision

boxes and the required state transitions.

Design requirements of data processor can be

obtained from the operations specified with the state

and conditional boxes.

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ASM Chart => Controller

Procedure:
Step 1: Identify all states and assign suitable codes.
Step 2: Draw state diagram.
Step 3: Formulate state table using

State from state boxes

Inputs from decision boxes
Outputs from operations of state/conditional boxes.
Step 4: Obtain state/output equations and draw circuit.

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ASM Chart => Controller

T0

T0

Initial state

T1

T2

T1

Assign codes to states:

T0 = 00
T1 = 01
T2 = 11

A 0
F 0

A A+1
0

A2

E 0

E 1
0

A3
T2

1
F 1

Inputs from conditions in decision boxes.

Outputs = present state of controller.

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ASM Chart => Architecture/Data

Processor

Architecture is more difficult to design than controller.

Nevertheless, it can be deduced from the ASM chart.
In particular, the operations from the ASM chart
determine:
What registers to use
How they can be connected
What operations to support
How these operations are activated.

Guidelines:
always use high-level units
simplest architecture possible.

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ASM Chart => Architecture/Data

Processor
Various operations are:

Counter incremented (A A + 1) when state = T1.

Counter cleared (A 0) when state = T0 and S = 1.
E is set (E 1) when state = T1 and A2 = 1.
E is cleared (E 0) when state = T1 and A2 = 0.
F is set (F 1) when state = T2.

Deduce:
One 4-bit register A (e.g.: 4-bit synchronous counter with

clear/increment).
Two flip-flops needed for E and F (e.g.: JK flip-flops).

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ASM Chart => Architecture/Data

Processor

start

A3

(A
A + 1) when state = T1.
(A 0) when state = T0 and S = 1.
(E 1) when state = T1 and A2 =
1.

T0
Controller

T1

Clk
A2

T2
J

K
J
A4

A3

A2

4-bit syn.
counter A

A1

count
CP
clear

clock

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Implementing Controller:
Decoder + D Flip-flops
Flip-flop input functions:
DG1 = T1.A2.A3
DG0 = T0.S + T1

Circuit:

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Algorithmic State Machine and

DataPath (ASMD) Chart

ASMD is different from ASM in that each of the

transition path of an ASM is annotated with the
associated concurrent register operations of datapath

ASM vs. ASMD charts for a counter with enable

ASM chart
representation

ASMD chart
representation

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ASMD Chart for 4-bit Counter

A 4-bit counter that can count up, count down or hold

the count

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ASMD Chart for 4-bit Counter

Simplified ASMD Chart

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ASMD Chart for 4-bit Counter

Asynchronous Reset

Synchronous Reset

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2:1 Decimator

Decimators are used in digital signal processors to

move data from a high-clock-rate datapath to a lowerclock-rate datapth.

They are also used to convert data from a parallel

format to a serial format.
Two-Stage Pipeline as 2:1 Decimator

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2:1 Decimator

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Ones Count Circuit

A circuit that counts the 1s in a word and terminates

activity as soon as possible.

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