VHDL

Tutorial 1
Signal Processing, CE00039-2

Digital Systems CE00057-6

Shortly About the VHDL

VHDL is an acronym of VHSIC
Hardware Description Language
VHSIC is an acronym of Very High
Speed Integrated Circuits
A Formal Language for Specifying the
Behavior and Structure of a Digital
Circuit
Signal Processing, CE00039-2

Digital Systems CE00057-6

Introduction
Two major HDLs:
VHDL
standardized by IEEE in 1987,1993, 2002, 2006
object-oriented, very widely used
Has Verbose syntax like Ada
Verilog
standardized by IEEE in 1995, 2001, 2005
has concise syntax like C

Signal Processing, CE00039-2

Digital Systems CE00057-6

ModelSim XE II 5.7g

Signal Processing, CE00039-2

Digital Systems CE00057-6

ModelSim XE II 5.7g

Signal Processing, CE00039-2

Digital Systems CE00057-6

ModelSim XE II 5.7g

Signal Processing, CE00039-2

Digital Systems CE00057-6

ModelSim XE II 5.7g

Signal Processing, CE00039-2

Digital Systems CE00057-6

ModelSim XE II 5.7g

Signal Processing, CE00039-2

Digital Systems CE00057-6

ModelSim XE II 5.7g

Signal Processing, CE00039-2

Digital Systems CE00057-6

ModelSim XE II 5.7g

Signal Processing, CE00039-2

Digital Systems CE00057-6

ModelSim XE II 5.7g

Signal Processing, CE00039-2

Digital Systems CE00057-6

ModelSim XE II 5.7g

Signal Processing, CE00039-2

Digital Systems CE00057-6

VHDL

Tutorial 2
Signal Processing, CE00039-2

Digital Systems CE00057-6

Hardware abstraction

Signal Processing, CE00039-2

 External view specifies the interface of the

device through which it communicates with
other models in its environment.
Internal view specifies the
functionality/structure of the device.
The hardware abstraction of any digital system
is called Entity.

Signal Processing, CE00039-2

Primary design units

To describe an entity, there are 5
primary design units;
1) Entity declaration
2) Architecture body
3) Configuration declaration
4) Package declaration
5) Package body
Plus library declaration
Signal Processing, CE00039-2

Entity & its model

Signal Processing, CE00039-2

Library declaration: syntax

Library library_name;
Use library_name.package name.package
parts;
library

packages

ieee library

Std_logic_1164
Std_logic_arith
Std_logic_signed
Std_logic_unsigned

Signal Processing, CE00039-2

Entity declaration: syntax

Entity entity_name is
Port(
port_name:signal mode signal type;
.
.
);
End entity_name;

Signal Processing, CE00039-2

Architecture body:syntax

architecture architecture_name of entity_name is

{declaration};
Begin
{code};
end architecture_name;

Signal Processing, CE00039-2

AND gate
library ieee;
use ieee.std_logic_1164.all;
entity and2 is
port(x,y:in std_logic;z:out std_logic);
end and2;
architecture data flow of and2 is
begin
z<= x and y;
end data flow ;
Signal Processing, CE00039-2

VHDL

Tutorial 3
Signal Processing, CE00039-2

Digital Systems CE00057-6

Architecture Body
There are 4 different ways of
modeling styles

1.
2.
3.
4.

Data flow modeling

Behavioral modeling
Structural modeling
Mixed modeling

Signal Processing, CE00039-2

Data flow Modeling

Usage of concurrent signal
assignment statements
Order independent
Eg: begin
x<=a and y;
q<=c and z;
z<=a and p;

Signal Processing, CE00039-2

 If an event occurs in a at time,

T:statement 1 & 3 will get triggered
at (T+) time
Then statement 2 will get triggered
at (T+2) time
Where 0ns (infinitesimally small)
is called delta delay

Signal Processing, CE00039-2

Behavioral Modeling
Usage of sequential signal assignment statements
Order dependent
Eg: OR GATE
begin
process(a,b)
begin
if a=0 and b=0 then
c<=0;
else
c<=1;
end if;
end process;
end architecture_name;

Signal Processing, CE00039-2

VHDL

Tutorial 4
Signal Processing, CE00039-2

Digital Systems CE00057-6

comparator
library ieee;
use ieee.std_logic_1164.all;
entity Comparator is
port( A: in std_logic;
B: in std_logic;
c: out std_logic_vector(0 to 1));
end Comparator;
architecture behv of Comparator is
begin
process(A,B)
begin
if (A<B) then
c <= "00";
elsif (A=B) then
c <= "01";
else
c <= "11";
end if;
end process;
end behv;

Signal Processing, CE00039-2

VHDL

Tutorial 5
Signal Processing, CE00039-2

Digital Systems CE00057-6

Signal & variable

signal

variable

Signal declaration starts with the

keyword
signal

Variable declaration starts with

the keyword variable

It is assigned a value after a

certain delta delay

It is assigned a value
instantaneously

Assignment operator is <=

Assignment operator is :=

Signals not declared within the

process

Variables are declared within the

process

Signal Processing, CE00039-2

Usage of signals
library ieee;
use ieee.std_logic_1164.all;
entity aoi is
port(
a,b,c,d: in std_logic;z:out std_logic);
end aoi;
architecture data of aoi is
signal l,m,n:std_logic;
begin
l<=a and b;
m<=c and d;
n<=l or m;
z<=not n;
end data;

Signal Processing, CE00039-2

Usage of variables
library ieee;
use ieee.std_logic_1164.all;
entity aoi is
port(
a,b,c,d: in std_logic;z:out std_logic);
end aoi;
architecture behv of aoi is
begin
process(a,b,c,d)
variable l,m,n:std_logic;
begin
l:=a and b;
m:=c and d;
n:=l or m;
z<=not n;
end process;
end behv;

Signal Processing, CE00039-2

ALU
library ieee;
use ieee.std_logic_1164.all;
entity ALU is
port(
A:
in std_logic_vector(1 downto 0);
B:
in std_logic_vector(1 downto 0);
Sel: in std_logic_vector(1 downto 0);
Res: out std_logic_vector(1 downto 0) );
end ALU;
architecture behv of ALU is
begin
process(Sel)
begin
case Sel is
when "00" =>
Res <= A or B;
when "01" =>
Res <= A and B;
when "10" =>
Res <= A nand B;
when "11" =>
Res <= A nor B;
when others =>
Res <= "XX";
end case;
end process;
end behv;
Signal Processing, CE00039-2

VHDL

Tutorial 6
Signal Processing, CE00039-2

Digital Systems CE00057-6

Structural modeling
architecture HA_STRUCTURE of HALF_ADDER is
component XOR2
port (X, Y: in BIT; Z: out BIT);

end component;
component AND2
port (L, M: in BIT; N: out BIT);

end component;
begin
X1: XOR2 port map (A, B, SUM);
A1: AND2 port map (A, B, CARRY);
end HA_STRUCTURE;
Signal Processing, CE00039-2

 The first component instantiation statement, labeled XI, shows

that signals A and B (the input ports of the HALF_ADDER),
are connected to the X and Y input ports of a XOR2
component, while output port Z of this component is
connected to output port SUM of the HALF_ADDER entity.
Similarly, in the second component instantiation statement,
signals A and B are connected to ports L and M of the AND2
component, while port N is connected to the CARRY port of
the HALF_ADDER.

Signal Processing, CE00039-2

VHDL

Tutorial 7
Signal Processing, CE00039-2

Digital Systems CE00057-6

 Write a vhdl program to implement a

half adder using data flow,
behavioral and structural modeling?

Signal Processing, CE00039-2

VHDL

Tutorial 8
Signal Processing, CE00039-2

Digital Systems CE00057-6

 Write a vhdl program to implement a

full adder using data flow,
behavioral and structural modeling?

Signal Processing, CE00039-2

VHDL

Tutorial 9
Signal Processing, CE00039-2

Digital Systems CE00057-6

 Write a vhdl program to implement a

half subtractor using data flow,
behavioral and structural modeling?
Write a vhdl program to implement a
full subtractor using data flow,
behavioral and structural modeling?

Signal Processing, CE00039-2

VHDL

Tutorial 10
Signal Processing, CE00039-2

Digital Systems CE00057-6

 Write a vhdl program to implement a

3*8 decoder using data flow,
behavioral?
Write a vhdl program to implement a
8*3 encoder using data flow,
behavioral?

Signal Processing, CE00039-2