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Mac

The document describes the design of a low power, high speed multiplier-accumulator (MAC) unit for digital signal processing applications. A MAC unit performs multiplication and accumulation operations and consists of a multiplier and accumulator. The designed MAC uses a modified Wallace tree multiplier and carry save adder. It operates at 217MHz with a power dissipation of 177.732mW. The MAC unit is well suited for applications like signal filtering that require fast processing of large amounts of data.

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194 views20 pages

Mac

The document describes the design of a low power, high speed multiplier-accumulator (MAC) unit for digital signal processing applications. A MAC unit performs multiplication and accumulation operations and consists of a multiplier and accumulator. The designed MAC uses a modified Wallace tree multiplier and carry save adder. It operates at 217MHz with a power dissipation of 177.732mW. The MAC unit is well suited for applications like signal filtering that require fast processing of large amounts of data.

Uploaded by

deepakk_alpine
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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INTRODUCTION:

With the recent rapid advances in multimedia and communication systems, realtime signal processing like audio signal processing, video/image processing, or largecapacity data processing are increasingly being demanded.

The multiplier and multiplier-and-accumulator (MAC) are the essential

elements of the digital signal processing such as filtering, convolution,


transformations and Inner products
Power dissipation is recognized as a critical parameter in modern the objective
of a good multiplier is to provide a physically compact, good speed and low power
consuming chip.

AIM Of the Project:


MAC unit is used for high performance digital signal processing systems. The
DSP applications include filtering, convolution, and inner products.
multiplier-and-accumulator (MAC) for high speed and low-power by adopting the
new SPST implementing approach.
Therefore the functionality of the MAC unit enables high-speed filtering and
other processing typical for DSP applications.
MAC is a integrating circuit that reduces the power consumption , delay & area.

MAC INTRODUCTION:
MAC unit performs important operation in many of the digital signal
processing (DSP) applications.
The multiplier is designed using modified Wallace multiplier and
the adder is done with carry save adder.
The total MAC unit operates at 217 MHz. The Total power dissipation is
177.732mW.
In this project we used Modelsim for logical verification, and further
synthesizing it on Xilinx-ISE tool

MAC basic architecture:


A MAC unit consists of a
multiplier & an accumulator
containing the sum of the
previous successive products.
The MAC inputs are
obtained from the memory
location and given to the
multiplier block.

The design consists of 64 bit modified Wallace multiplier.


128 bit carry save adder and a register/ accumulator.
The output of carry save adder is 129 bit i.e. one bit is for the carry
(128bits+ 1 bit). Then, the output is given to the accumulator register.
The accumulator register used in this design is Parallel In Parallel Out
(PIPO).
The output of the accumulator register is taken out or fed back as one of
the input to the carry save adder.

Wallace tree:
A Wallace tree is an efficient hardware implementation of a digital circuit
that multiplies two integers.
Generally in conventional Wallace multipliers many full adders and half
adders are used in their reduction phase

CARRY SAVE ADDER:


A carry-save adder is a type of digital adder, used in computer micro architecture to
compute the sum of three or more n-bit numbers in binary. It differs from other
digital adders in that it outputs two numbers of the same dimensions as the inputs,
one which is a sequence of partial sum bits and another which is a sequence of carry
bits.

The carry save adder block is same as the full


adder

Carry Save Adder (adding 2 numbers)

In this design 128 bit carry save adder is used since the output of

the multiplier is 128 bits .


The entire sum can be calculated by shifting the carry sequence left
by one place and then appending a 0 to most significant bit of the
partial sum sequence.
a carry-save adder produces all the output values in parallel,
resulting in the total computation time less than ripple carry adders.
So, Parallel In Parallel Out (PIPO) is used as an accumulator in the
final stage.

RESULT:

Output at reset condition:

Applications
1) digital signal processing (DSP) applications
a. Signal filtering
b. convolution.
c. Decreasing number of inner products.
2) Optical communications.
3) Multimedia image processing.
4) real-time signal processing like audio signal processing, video/image
processing, or large-capacity data processing

Advantages:
The MAC unit operates completely independent of the CPU, it can process
data separately and there by reduce CPU load. The application like optical
communication systems which is based on DSP , require extremely fast
processing of huge amount of digital data

Area , Delay Report & power


dissipation of Different MAC unit

Conclusion:
Since the delay of 64 bit is less, this design can be used in the system
which requires high performance in processors involving large number of
bits of the operation. The MAC unit is designed using Verilog-HDL and
synthesized in Cadence 180nm RTL Complier.

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