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Switched Capacitor DC-DC Converters: Topologies and Applications

This document outlines various switched capacitor DC-DC converter topologies and their applications. It begins with motivations for inductorless converters and describes the ideal Dickson charge pump circuit. It then discusses non-idealities and modified Dickson topologies that address threshold voltage drops. These include using static transfer switches and clocked transistors to drive the switches. Applications discussed include generating high voltages for flash memory programming and using charge pumps to sample input signals for analog-to-digital converters or bias low-voltage amplifiers above threshold voltages. In conclusion, it compares different Dickson variants and discusses capacitor sizing, cross-coupled doublers, and full H-bridge converters found in commercial products.

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Nitu Vlsi
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82 views25 pages

Switched Capacitor DC-DC Converters: Topologies and Applications

This document outlines various switched capacitor DC-DC converter topologies and their applications. It begins with motivations for inductorless converters and describes the ideal Dickson charge pump circuit. It then discusses non-idealities and modified Dickson topologies that address threshold voltage drops. These include using static transfer switches and clocked transistors to drive the switches. Applications discussed include generating high voltages for flash memory programming and using charge pumps to sample input signals for analog-to-digital converters or bias low-voltage amplifiers above threshold voltages. In conclusion, it compares different Dickson variants and discusses capacitor sizing, cross-coupled doublers, and full H-bridge converters found in commercial products.

Uploaded by

Nitu Vlsi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Switched Capacitor DC-DC

Converters: Topologies and


Applications
Bill Tsang and Eddie Ng

Outline
Motivations
Dicksons Charge Pump
Other Various Charge Pumps
Applications
Conclusion

Motivations
Inductorless
On-chip integration
Low cost
High switching frequency
Easy to implement (open-loop system)
Fast transient but large ripple
High efficiency but limited output power

Ideal Dicksons Charge


Pump(Phase 1)
2VDD-Vt

VDD

VDD-Vt
VDD-Vt

VDD

VDD-Vt

0
VDD

C1

clk

clk_bar

Clk=0, Clk_bar=VDD
Finite diode voltage drops, Vt

Vo
C2

C3

Ideal Dicksons Charge


Pump(Phase 2)
3VDD-2Vt
2VDD-Vt

VDD

2VDD-2Vt

VDD-Vt
VDD

Vo

VDD-Vt
VDD

clk

clk_bar

C1

C2

C3

Clk=VDD, Clk_bar=0
Maximum voltage stress on diodes 2VDD-Vt => reliability issue
Maximum voltage stress on capacitors VCn =n(VDD-Vt) => reliability issue

Dicksons Charge Pump


V2+dV2

V1+dV1

V2

V1

v1

Vth

v2

VDD

Vo
Cp

C1

Cp

C2

Cp

C3

C1=C2=C3=C

clk

clk_bar

V V
V Vth

C
Io

C C p f (C C p )

(Body effect can be significant at later stages)

Vout VDD N * (V Vt ) Vt

Non-idealities
Threshold voltage drop
operation]

[Mos charge pumps for low-voltage

Vth Vtho VBS 2F 2F

Parasitic capacitor divider voltage


drop
GV 2 V2 V1 efficiency
V Vtn (V2 ) and
Low conversion
pumping gain
2
Limited maximum number
of stages
VDD Vtho

Vout,max
2F 2F

[An on-chip High-voltage generator circuit for


EEPROMs with a power supply voltage below 2V]

Modified Switch
MD1
VDD

MD1
VDD

MS1

CTS

clk

2VDD

clk

Static Charge Transfer Switches (CTS)


Eliminate transistor threshold drop

Modified Dicksons Charge Pump #1 (NCP1)


dV

v3

dV

V2
dV

v1
MD1

MD2

v1

MD3

v2

MD4

v3

Vo

VDD

MS1

MS3

MS2

MS4

Cp

Cp
Cp

C1

Cp

C2

Cp

C3

C4

C5

clk

Conditions:

clk_bar

1, Clk=Vdd,Clk_bar=0: v2, v3+V


To turn on transistor Ms2; Vgs = 2V

2 * V Vtn (V2 )

2, Clk=0,Clk_bar=VDD: v1, v2+V,v3


To turn off transistor Ms2; Vgs = 2V

2 * V Vtn (V1 )

impossible

Modified Dicksons Charge Pump


#1 (NCP-1)
Static Charge Transfer Switches (CTS)
Better voltage pumping gain than diodes
GV 2 V2 V1 V

Lower voltage equals upper voltage of


pervious stage
Utilizing higher voltage from following
stage to drive CTS
Reverse charge sharing since CTS cannot
turn off completely

Modified Switch #2
MD1

MS1

MN1 used to turn off MS1

MP1 used to turn on MS1


MN1

MP1

Next
stage

clk

Eliminate transistor threshold drop


Complete turn-off of switch, MS1

Modified Dicksons Charge Pump #2 (NCP2)


dV

dV

dV

MD1

MS1

v2

C1

v3

MS3

MS2

MN2

Cp

MD3

MD2
v1

MP2

Cp

C2

Cp

C3

clk

clk_bar

Conditions:
1, Clk=Vdd,Clk_bar=0: v2, v3+V
To turn on transistor MP2 and MS2; Vgs = 2V

2 * V Vtp

2 * V Vtn (V2 )

2, Clk=0,Clk_bar=VDD: v1, v2+V,v3


To turn on transistor MN2 and turn off MS2; Vgs = 2V

2 * V Vtn (V1 )

Complete Circuit(NCP-2)
dV
dV
dV

MD1

v2

v1

MS1

MD3

MD2

MS3

MS2

MD4
v3

Vo

MS4

MN2

MP2

Cp
Cp
Cp

C1

Cp

C2

Cp

C3

clk

clk_bar

Careful PMOS well connection to prevent latch-up


Diode-connected output stage used

C4

C5

Modified Dicksons Charge


Pump #3 (NCP-3)

NCP-3 uses boosted clock at output


stage
dV

dV

dV

MD1

MD3

MD2

MD4

Vi

Vo

MS1

MS3

MS2

MS4

C5

HV
Clock
Generator

clk
Cp
Cp
clk

clk_bar

C1

Cp

C2

Cp

C3

C4

Converters Output Voltage


Results

Optimum Capacitance
Selection
C
I
V V

DD

Vout VDD N * V

out

Ci C p

f (Ci C p )

Ctot N * Ci

C C V

out

VDD

CiVDD I out / f

Ci

Ctot 2Ci C p CiVDD I out / f Ci Ci C p VDD

(Vout VDD )
2
Ci
CiVDD I out / f
Ci ,min

I
I
out out
VDD f
VDD f

C p I out
VDD f

[A Low-Ripple Switched-Capacitor DC-DC Up converter for Low-voltage applications]

Efficiency and Output


Impedance
Power loss due to: Vth, Rds(on), ESR,
Cp, etc

[Performance limits of switched-capacitor DC-DC Converter]

Efficiency estimation

Vout
M *Vin

M=ideal conversion ratio

Output impedance (slow switching)


[Performance limits of switched-capacitor DC-DC Converter]

i Ts
Ro

Vout
1

q / Ts
fC

Ts=switching period
i= parasitic time constant
q=charge supplied to the source Vout

Cross-Coupled Charge
Pump
2Vdd RL
Vo
RL Rds ( on )

Vripple

I
L
2f

VDD

M10

M9

1
1

C L C1 C L

Vo
1
sC1 sC L
I L
RL

Vo

1
C1

RL

CL1

C2

phi2
phi1

PMOS to transmit 2VDD to output


Bodies tied to source(highest voltage) to
avoid forward biasing junction diodes
[Area-efficient CMOS Charge Pumps for LCD Drivers]

H-bridge Topology
1
Commercial
products (Linear
Technology,
Fairchild, Maxim
)
3
Buck or Boost
functions
Negative voltage
generation

Oscillator and Control

H-bridge Topologies
1

Vin

Phase 1: transistors in red are on


Phase 2: transistors in blue are on

Vin

4
Vout

doubler

phi1

phi2

phi1
phi2

Vout = 2Vin
Vout

Vin

Vin

Vout

phi1

inverter

phi2

phi1
phi2

Vin

Vout = -Vin

phi1

Splitter

phi2

Vout = 0.5 Vin

phi1
phi2

Application (1): Flash


Memory
Floating gate programming
Control gate voltage >> Vdd

[ee141 lecture]

Application (1): Flash


Memory
Nominal VDD= 5V

Application (2): Sample Switches


vicm

vicm
phi1

phi2d

Ci

Vi+

S/H circuit
constant vgs
sampling with all
input level
Reduces
distortion
Reduces
Rds(on)
Voltage

phi1d

CL

phi2

Cs

Vo+

OTA
+

Cs

phi1d

Vo-

phi2

Vi-

CL
phi2d

phi1

vicm

Ci

vicm

VDD
M10

M9

Phi_bar

M4

M5

M8
M3
M7
C1

C2

C3

doubler

M2
Phi

M1
M9

M6

M11
Vo
VSS

Phi_bar
Vin

Application (3): Low


voltage Amplifier
Positive zero in
Miller
compensation
1/gm pole-zero
cancellation

VDD

Charge pump

[charge-pump

assisted low-power/low-voltage CMOS Opamp Design]

V-

V+

>2VGS

Conclusion
Different Dicksons SC converters
discussed
Optimal Capacitor size selection
Discussion of cross-coupled doublers
Commercial product: Full H-bridge
Applications: Flash, ADC, Amplifier,
LCD driver

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