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Design Rules-Vlsi

The document provides design rules for wiring and transistor layout in CMOS processes. Some key points: - Diffusion, poly, metal 1, and metal 2 wiring have minimum spacing rules of 2λ, 3λ, 3λ, and 4λ respectively. - Transistors have minimum size and spacing rules such as polysilicon extending 2λ beyond diffusion boundaries and 2λ minimum separation between features. - Contacts between layers have overlap areas with centered cuts, such as metal 1 to polysilicon using a 2λx2λ cut within a 4λx4λ overlap area. - P-well CMOS processes have special rules for VDD and VSS contacts to n-

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Prabhat Kumar
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1K views9 pages

Design Rules-Vlsi

The document provides design rules for wiring and transistor layout in CMOS processes. Some key points: - Diffusion, poly, metal 1, and metal 2 wiring have minimum spacing rules of 2λ, 3λ, 3λ, and 4λ respectively. - Transistors have minimum size and spacing rules such as polysilicon extending 2λ beyond diffusion boundaries and 2λ minimum separation between features. - Contacts between layers have overlap areas with centered cuts, such as metal 1 to polysilicon using a 2λx2λ cut within a 4λx4λ overlap area. - P-well CMOS processes have special rules for VDD and VSS contacts to n-

Uploaded by

Prabhat Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Design rules for wires(NMOS and CMOS)

Diffusion Rules
2

Metal 1 Rules
3

Poly Rules

Metal2 Rules
4
2

4
2

1
diff

Transistor Design rules(NMOS,PMOS and CMOS)


Minimum size
transistors

Diffusion is not
to decrease in
width < 2 from
polysilicon

Separation from
contact cut to transistor
Implant for an NMOS
Depletion mode transistor to
extend 2 min. beyond
channel in all direction (and
beyond polysilicon with
buried contact

2 min.

2 min.

Polysilicon to extend a
min. of 2 beyond
diffusion boundaries
(width constant)

2 min.

2 min.

Extension and separations


22

2
22

66
2

NMOS(enhancement)

PMOS(enhancement)

implant

NMOS(depletion)

Contacts( NMOS and CMOS)


1. Metal 1 to polysilicon or to diffusion

3 min.
22 cut centered on 44
superimposed areas of layers to be
joined in all cases

2
2 min.

Min. separation
multiple cuts

2. Via(contact from metal 2 to metal 1 and thence to other layers


2 min. separation (if
other spacings allow)

via
Metal 2
cut

Via and cut used to


connect metal 2 to
diffusion
44 Area of overlap
with 22 via at center

Metal 1

via

cut

BURIED CONTACT

BASICALLY , LAYERS ARE JOIN ED OVER A 2x 2 AREA WITH THE


BURIED CONTACT CUT EXTENDING BY 1 IN ALL DIRECTION
AROUND THE CONTACT AREA EXCEPT THAT THE CONTACT CUT
EXTENSION IS INCREASED TO 2 IN DIFFUSION PATHS LEAVING THE
CONTACT AREA. THIS IS TO AVOID FORMING UNWANTED
TRANSISTORS

Contacts polysilicon to diffusion(NMOS only in the main text)


Special case
eg. Pull-up
transistor in
NMOS
(implant not
shown)

1.Buried contact
1
2
2

2
1 1

Channel
length L

1 1

S*
1

Unrelated polysilicon
or diffusion

2.Butting contact
Special case
eg. Pull-up
transistor in
NMOS
(implant not
shown)

* Obey separation rule

Channel
length L

Butting contact shown


without metal lid for
clarity

Design rules for wires(Orbit 2m CMOS)


N diffusion

Note: N diff. and P.diff cannot cross or join


P diffusion

3m

2m

N diffusion

P diffusion

S=2.5m

3m

2m
1m

S
polysilicon1

1.5m

Polysilicon 2

2m

2m

2.5m

polysilicon1

2m

Polysilicon 2

3m
2m

2m

1.5m min. edge to edge


1.5m min. edge to edge

2m

Poly. 2 overlapping poly. 1

2m
1.5m min. overlap

Poly. 1 overlapping poly. 2

Metal 1
2.5m
S=2.5m

Metal 1
2.5m

Metal 2
3m
3m

Metal 2
3m

Particular rules for P-well CMOS process


VDD and VSS contacts
P-well

To n-type features

VDD

P+ mask

VDD contact to
substrate

VSS

Metal(pattern omitted for


clarity)

VSS contact to P-well

P+ mask

(2 2) cut on 4 4
overlap area

To p-type features

2
4

3
2

VDD

VSS
P+ mask

P-well

P+ mask
3

Note: Split contacts may also be made with


separate cuts.

P-well and P+ mask rules

S = 2 min. for wells at same potential


S = 2 min. for wells at different potentials

3
2

5
1 2
Min. spacing to
external thinox

1 2

2 2
P-well must overlap 3 all enclosed thinox by
min. as shown. Thinox must not cross well
boundary.
Min. width = 4

P+ mask minima:
1 Overlap of thinox
2 Seperation to channel
3 Seperation P+ to P+
4 Spacing from unrelated
thinox

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