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Memory Built in Self Testing

Introduction to memory BIST (BUILT In SELF TESTING). It gives introduction for different memory types and their testing technniques

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ShereenHussein
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62 views

Memory Built in Self Testing

Introduction to memory BIST (BUILT In SELF TESTING). It gives introduction for different memory types and their testing technniques

Uploaded by

ShereenHussein
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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31 December 2014

Testing of Digital Systems - Memory BIST - Group


10

MEMORY BUILT-IN-SELF-TESTING

AGENDA
Introduction for Memory BIST
Types of Memory Used in BIST

ROM
RAM

Effective Distributed BIST Architecture for RAMs

Architecture

Diagnosis

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

INTRODUCTION - BIST

BIST is a methodology of making a system test


itself.

The main purpose of BIST is to reduce complexity.

Digital Systems with BIST have a reduced testing


cost.

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

INTRODUCTION MEMORY BIST

The first MBIST approach was with a serial


interconnection scheme.

For complex SOC, it is extended to hardware/software


co-testing memory BIST.

By using existing on-chip resources, we can:


Save area overhead
Eliminate performance penalty for bus-connected memories.

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

INTRODUCTION - GENERAL ARCHITECTURE OF


MEMORY BIST
Test Pattern
Generator
(TPG)

Device
Under Test
(DUT)

Output
Response
Analyzer (ORA)

Responsible for
generating test
patterns.

DUT can be the


entire chip or
only a part of the
chip

Analyzes the test


results compared
with a reference.

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

INTRODUCTION - TYPES OF SELF-TESTING


MBIST procedure can perform in 3 ways:
Concurrent
The memory is
tested
simultaneously
during its normal
operation time.
It detects and
corrects on-fly
faults.

Non-Concurrent
The memory is
tested in a special
test mode
BIST algorithm can
process faster and
more freely.

Transparent
The memory is
interrupted during
its normal
operation time
This method
requires extra area
for the storage of
memory content
6

Testing of Digital Systems - Memory BIST - Group


10

31 December 2014

MEMORY TYPES ROM - BIST

ROM has the initialization code of the system


stored in them.

BISTs for ROMs do not involve any write-data


stepper

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

MEMORY TYPES RAM - BIST

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

FSM - BIST

In order to verify whether a given memory cell is good, it


is necessary to conduct a sequence of write and read
operations to the cell. The actual number of read / write
operations and the order of the operations depend on the
target fault model.

Most commonly used memory test algorithms are March


tests, in which there are finite sequences of March
elements. A March element is a finite sequence of read (r)
or writes (w) operations applied to a cell in memory
before processing the next cell.
9

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

FAMOUS ALGORITHMS

10

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

DESCRIPTION OF MATS-PLUS ALGORITHM

11

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

DESCRIPTION OF MATS-PLUS ALGORITHM

The first state of this algorithm is Idle state.

The BIST operation start as soon as BIST_En signal is made equal


to 1 then in this algorithm the first operation is W0 which
means that there is write 0 operation is to be performed hence
S0 is the first state in which write 0 operation performed.

When write_complete signal equal to 1 then FSM entered in


new state S1. In S1 state there are two elements, one is r0
and another is W1.When write one operation is performed then
write_complete signal become equal to 1 then FSM will switch
to S2 state, where two operation required to be performed; read
one and write zero.

Thus when the last operation is completed then FSM will switch to
idle state.
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Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

EFFECTIVE DISTRIBUTED BIST ARCHITECTURE


FOR RAMS
Difficulties

of testing distributed memories on

one chip

Small size
Spatially distributed
Deeply embedded inside the chip
Different sizes

Solution
13

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

BIST ARCHITECTURE FOR DISTRIBUTED RAMS


Single BIST
Processor

Wrapper
Minimal set of
communication
signals

Scan chain

Micro-programmable machine executing


elementary test primitives

Around each SRAM


Including an address generator, a background
pattern generator, and a comparator

Execute and synchronize the test algorithm

Connecting all the Wrappers


Allows full diagnosis
14

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

THE BIST PROCESSOR

Test algorithm (a March Algorithm) is stored in a


dedicated microProgram-Memory
coded using a set of test primitives.

BIST

Processor :

reads one test primitive at a time


forwards it to all the Wrappers of the SRAMs under
test using a synchronization signal
waits for all the enabled SRAMs to complete the test
primitive before sending the next one.
15

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

THE BIST PROCESSOR

The set of test primitives needed to code a March


Algorithm

16

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

THE BIST PROCESSOR

Example:
MATS algorithm for an 8-bit wide RAM

where BP0 through BP7 are taken from the set of


Background Patterns from the table below

17

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

THE BIST PROCESSOR

Described using the


following sequence of
primitives:

18

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

SCHEDULING

Problem

Solution

The wide variety of SRAMs that can be


found in a complex architecture may
require different test algorithms.

Select the set of memories to be


placed under test

19

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

SCHEDULING - SCHEDULING USING THE CONF


PRIMITIVE

Where:
Conf is the primitive opcode;
#words is the number of 4-bit words used to code the
ActivationMask;
ActivationMask is a mask of bits, one for each memory in
the system. To include a memory in the set of the SRAMs
under test the corresponding bit in the ActivationMask
20
has to be set.

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

SCHEDULING - SCHEDULING USING THE CONF


PRIMITIVE

Example
The first ActivationMask
sets the RAM1 and
RAM4 under test
whereas the second one
sets the RAM2 and
RAM3 under test.

21

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

SCHEDULING - USING THE SCAN CHAIN OPTION

Loading the appropriate ActivationMask directly from


the extern using a scan chain protocol.

22

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

MEMORY WRAPPERS

Execute the test primitives received by the BIST


Processor.

Generates the correct test patterns and memory


addresses required to execute the received test primitive.

Evaluates the output results of a read-and verify


primitive.

23

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

MEMORY WRAPPERS

The internal structure of a Wrapper:

24

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

MEMORY WRAPPERS

Address Generator (AG) is in charge of generating the correct


address where the test pattern, provided by the Background
Pattern Generator (BPG), has to be written or verified.

The correctness of the content of a memory cell is evaluated using


a simple comparator.

Two Status Bits are used to set the memory in transparent or in


test mode (the Mode Status Bit) and to store the test results at the
end of the BIST algorithm (the Result Status Bit), respectively.

Finally, each Wrapper includes an Interface Block able to receive


the test primitives from the BIST Processor, and to produce the
status signals needed by the BIST Processor to schedule the next
test primitive to be executed.
25

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

MEMORY WRAPPERS

In particular, the Interface Block generates the following


information:

End of Instruction (EOIN): asserted when the last received


test primitive is thoroughly executed;

End of Address Space (EOAD): asserted when the


address generator reaches the end of its addressing space;

End of Patterns (EOPG): asserted when the BPG has


generated the whole set of background patterns;

Read-and-Verify Result (GO): asserted when the content of


the addressed memory cell matches the value expected by
the test algorithm.
26

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

DIAGNOSIS

If the RAM is not


faulty

Only the Result_Status_Bit


(whose value is equal to
0) is placed on the scan
chain
Testing of Digital Systems - Memory BIST - Group 10

If the RAM is
faulty

The Result_Status_Bit
(whose value is 1) is
concatenated to the
contents of the AG and
the BPG

27

31 December 2014

CONCLUSION
Distributed
BIST

Testing

Area overhead
minimized

28

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

ANY QUESTIONS
29

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

THANK YOU
30

Testing of Digital Systems - Memory BIST - Group 10

31 December 2014

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