Scribd
Upload
592 views

Image Processing Verilog

This document describes a project to implement a low-cost FPGA-based image processing solution with a small footprint. The existing system uses CPU processing which can be slow for real-time image processing applications. The project implements reading an image file into an FPGA and displaying it on a screen. It includes blocks for a VGA controller, image ROM, and results showing the RTL implementation and image displayed on screen. Future work will implement OpenCV algorithms for image thresholding and blob analysis on the FPGA.

Uploaded by

goutamkg
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
592 views

Image Processing Verilog

This document describes a project to implement a low-cost FPGA-based image processing solution with a small footprint. The existing system uses CPU processing which can be slow for real-time image processing applications. The project implements reading an image file into an FPGA and displaying it on a screen. It includes blocks for a VGA controller, image ROM, and results showing the RTL implementation and image displayed on screen. Future work will implement OpenCV algorithms for image thresholding and blob analysis on the FPGA.

Uploaded by

goutamkg
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 18

DEPT.

of E&C BVBCET

Low cost image processing hardware


with lowest footprint

Under the guidance of

Dr.R.B.Shettar
By Goutam
[2BV13LDE07]

Contents

Introduction

Block diagram of existing system


Disadvantages in existing system
Problem Definition
I phase of the project

VGA controller
Results
Conclusion
Future Implementation
References

Introduction

Image processing requires high computationally operation most of


these are done with software using CPU processing.
Software based image processing requires expensive and powerful
CPUs to perform real-time image processing, making it out of reach
for most robotic applications.
This is where a low cost FPGA based image processing solution
becomes useful.
This project implements such an image processing solution in
hardware, using a FPGA(spartan-6).

Block diagram of existing system

1 is conveyor
2 is power drive
3 is light source and CCD camera
4 is pneumatic segregator and compressed air tank

5 is control unit
6 is microcomputer

Disadvantages in existing system

In the existing system CPU processing is done and in some


machines Processors with DSP cores are used .Due to
execution is sequentially, in real time image processing
where time is critical, these processors will have delay in
getting output.
This leads to slow down the whole process.
One of the important disadvantages is size will be large
and cost will be more.

Problem Definition

As the project is divided into two phase.

In first phase is to read the image file to the


FPGA and display the image to the screen .
In second phase we will implement the image
processing module and combine the both phase.

Block diagram of I phase of the project

Block Diagram of Image ROM

O/P

I/P
Jpeg
Image

Convert
to .COE
Using Matlab

IPCORE
ROM

Simulation

VGA controller
Horizontal synchronization

Horizontal synchronization

Display:The region where the pixels are actually displayed on the

Screen
Retrace:The region in which the electron beams return to the left
edge. The video signal should be disabled.
Right border:The region that forms the right border of the display

region. It is also known as the front porch.


Left border:The region that forms the left border of the display
region.It is also known as the back porch

Vertical synchronization

Vertical synchronization

Display:The region where the horizontal lines are actually


displayed on the screen.
Display:The region where the horizontal lines are actually
displayedon the screen.
Bottom border:Theregion that forms the bottom border of the
display region. It is also known as the front porch (i.e., porch
before retrace). The video signal should be disabled.
Top border:The region that forms the top border of the display
region.It is also known as the back porch (i.e., porch after
retrace). The video signal should be disabled.

Results

RTL level implementation

Image displayed on screen

Conclusion
This system plays a role as a real time specific display
application. It is very effective as this VGA Controller only needs new
data to change to other design display. Thus, FPGA-based VGA
controller might be a good choice. The I phase of project is implemented
successfully.

Future Implementation
This project will be continued for II phase ,it describes the
implementation of opencv algorithm based on sequential
connected component will implemented on FPGA and verify the
results with output results obtained from the opencv.The design
enables the processing step to be inserted in the pixel data path
from the image source to the video memory.
The modules below shown will be implemented:
1.

Auto threshold

2.

Blob analysis

References

1.

Chu, Pong P.\ EMBEDDED SoPC DESIGN WITH NIOS II


PROCESSOR AND VERILOG EXAMPLES" Wiley Publication, New
Jersey,2008 edition.

2.

Hong Jeong \ARCHITECTURES FOR COMPUTER VISION


FROMALGORITHM TO CHIP WITH VERILOG" Wiley Publication,
Singapore,2014 edition.

3.

D. G. Bailey, \DESIGN FOR EMBEDDED IMAGE PROCESSING


ON FPGA" Wiley Publication,2011 edition.

4.

Core Generator User guide\http://homepages.cae.wisc.edu/ece554/

5.

website/Xilinx/Coregenuserguide.pdf".

6.

For VGA display timings www.vesa.org

Thank You

You might also like