Delay Optimization

And
Logical Efforts

Delay in a Logic Gate

Delay has two components: d = f + p
f: effort delay = gh (a.k.a. stage effort)
Again has two components
g: logical effort
Measures relative ability of gate to deliver current
g 1 for inverter
h: electrical effort = Cout / Cin
Ratio of output to input capacitance
Sometimes called fanout
p: parasitic delay
Represents delay of gate driving no load
Set by internal parasitic capacitance
2

Effective Resistance for Delay Estimation

Shockley models have limited value
Not accurate enough for modern transistors
Too complicated for much hand analysis

Simplification:

Replace Ids(Vds, Vgs) with effective resistance R such that Ids = Vds/R in series
with a switch.
R averaged across switching of digital gate (i.e. during linear mode of
operation)
1
1 L
1
R

CoxW
Cox W (Vgs Vt)
L

(Vgs Vt)

Too inaccurate to predict current at any given time because Ids rolls off
with Vds increase and R decreases
But good enough to predict RC delay which is the product of driver
3
resistance and the load capacitance.

Switch Level RC Delay Model

Use equivalent circuits for MOS transistors
( Usually logic gates use minimum length devices for least delay,
area and power consumption)
Thus delay of the logic gate depends on the widths of transistors
and the capacitance driven by the gate.

Ideal switch + capacitance and ON resistance

Unit nMOS has effective resistance R, capacitance
C
Unit pMOS has effective resistance 2R(to 3R
due to lower mobility), capacitance C

Capacitance proportional to width

4
Resistance inversely proportional
to width

Equivalent RC circuit models

d

Input
capacitance
d
g k
s

kC

R/k

Output
capacitance

kC
2R/k

g
kC

kC
s

d
g k
s

kC
g

kC
d

UNIT Inverter Delay Estimate

Estimate the delay of a fanout-of-1 inverter

d = 6RC

Drawing Multiple Input Circuits That

Has Resistance Equal To Unit Inverter

4
2

4
2
2
1

Example: 3-input NAND

Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).
2

2
3
3

3-input NAND Caps

Annotate the 3-input NAND gate with gate and diffusion
capacitance.
2C
2C
2
2C

5C

2C
2

2C

2C
2

2C

3C

5C

3C

5C

3C

2C
2C

3
3
3

9C
3C
3C
3C

3C

Example: 3-input NAND

Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
2

9C
5hC
n2
3C

3 n1

h copies

3C

t pdr 9 5h RC
t pdf 3C R3 3C R3
11 5h RC

R
3

9 5h C R3 R3 R3
10

Contamination Delay
Best-case (contamination) delay can be substantially less
than propagation delay.
Ex: If all three inputs fall simultaneously
2

9C
5hC
n2
3C

3 n1
3

3C

tcdr

5
R
9 5h C 3 h RC
3
3

11

Delay Components
Delay has two parts
Parasitic delay
9 or 11 RC
Independent of load

Effort delay
5h RC
Proportional to load capacitance

12

Example
Sketch a 2-input NOR gate with selected transistor
widths so that effective rise and fall resistances are
equal to a unit inverters. Annotate the gate and
diffusion capacitances.

13

Delay Plots
2-input
NAND

Normalized Delay: d

Inverter
g=
p=
d=

g=
p=
d=

4
3
2
1
0
0

Electrical Effort:
h = Cout / Cin

=f+p
= gh + p

What about NOR2?

14

Computing Logical Effort

DEF: Logical effort is the ratio of the input capacitance of a

gate to the input capacitance of an inverter delivering the same

output current.

Measure from delay vs. fanout plots

Or estimate by counting transistor widths
2

2
A

Y
1
Cin = 3
g = 3/3

4
Y
1

Cin = 4
g = 4/3

Cin = 5
g = 5/3

15

Catalog of Gates
Logical effort of common gates
Gate type

Number of inputs
1

NAND

4/3

5/3

6/3

(n+2)/3

NOR

5/3

7/3

9/3

(2n+1)/3

4, 4

6, 12, 6

8, 16, 16, 8

Inverter

Tristate / mux

XOR, XNOR

16

Catalog of Gates
Parasitic delay of common gates
In multiples of pinv (1)
Gate type

Number of inputs
1

NAND

NOR

2n

Inverter

Tristate / mux

XOR, XNOR

17

Example: Ring Oscillator

Estimate the frequency of an N-stage ring oscillator

Logical Effort:
Electrical Effort:
Parasitic Delay:
Stage Delay:
Frequency:

g=1
31 stage ring oscillator in
0.6 m process has
h=1
frequency of ~ 200 MHz
p=1
d=2
fosc = 1/(2*N*d) = 1/4N
18

Example: FO4 Inverter

Estimate the delay of a fanout-of-4 (FO4) inverter
d

Logical Effort: g = 1
Electrical Effort: h = 4
Parasitic Delay: p = 1
Stage Delay: d = 5

The FO4 delay is about

300 ps in 0.6 m process

15 ps in a 65 nm process

19

Multistage Logic Networks

Logical effort generalizes to multistage networks
Path Logical Effort

G gi

Cout-path

Path Electrical Effort

Path Effort

F f i gi hi

10
g1 = 1
h1 = x/10

x
g2 = 5/3
h2 = y/x

Cin-path

y
g3 = 4/3
h3 = z/y
20

z
g4 = 1
h4 = 20/z

20

Multistage Logic Networks

Logical effort generalizes to multistage networks
Path Logical Effort G
g

Path Electrical Effort H

Path Effort

Cout path
Cin path

F fi gi hi

Can we write F = GH?

21

Paths that Branch

No! Consider paths that branch:
15

G
H
GH
h1
h2
F

5
=1
= 90 / 5 = 18
= 18
= (15 +15) / 5 = 6
= 90 / 15 = 6
= g1g2h1h2 = 36 = 2GH
22

15

90

90

Branching Effort
Introduce branching effort
Accounts for branching between stages in path

Con path Coff path

Con path

B bi

Note:

h BH
i

Now we compute the path effort

F = GBH
23

Multistage Delays
Path Effort Delay

DF fi

Path Parasitic Delay P pi

Path Delay

D di DF P

24

Designing Fast Circuits

D di DF P
Delay is smallest when each stage bears same effort

f gi hi F

1
N

Thus minimum delay of N stage path is

1
N

D NF P
This is a key result of logical effort
Find fastest possible delay
Doesnt require calculating gate sizes
25

Gate Sizes
How wide should the gates be for least delay?
f gh g CCoutin
gi Couti
Cini
f

Working backward, apply capacitance

transformation to find input capacitance of each
gate given load it drives.
Check work by verifying input cap spec is met.
26

Example: 3-stage path

Select gate sizes x and y for least delay from A
to B
x
y

x
A

45

27

45

Example: 3-stage path

x
x
A

y
45
y

45

Logical Effort
G = (4/3)*(5/3)*(5/3) = 100/27
Electrical Effort
H = 45/8
Branching Effort
B=3*2=6
Path Effort
F = GBH = 125
Best Stage Effort
f 3 F 5
Parasitic Delay
P=2+3+2=7
Delay
D = 3*5 + 7 = 22 = 4.4 FO4
28

Example: 3-stage path

Work backward for sizes
y = 45 * (5/3) / 5 = 15
x = (15*2) * (5/3) / 5 = 10

x
x
A P:
84
N: 4

P:
x 4
N: 6

y
45
45
P:
y 12
N: 3

B
B
45
45

29

Best Number of Stages

How many stages should a path use?
Minimizing number of stages is not always fastest

Example: drive 64-bit datapath with unit

inverter
Initial Driver

2.8

16

23

NF1/N

D =
+P
= N(64)1/N + N

Datapath Load
N:
f:
D:

30

64
1
64
65

64
2
8
18

64
3
4
15
Fastest

64
4
2.8
15.3

Derivation
Consider adding inverters to end of path
How many give least delay?

Logic Block:
n1Stages
Path Effort F

n1

D NF pi N n1 pinv
1
N

N - n1 ExtraInverters

i 1

1
1
1
D
N
N
N
F ln F F pinv 0
N

Define best stage effort

31

1
N

pinv 1 ln 0

Best Stage Effort

pinv 1 ln 0 has no closed-form

solution

Neglecting parasitics (pinv = 0), we find =

2.718 (e)
For pinv = 1, solve numerically for = 3.59

32

Review of Definitions
Term

Stage

Path

number of stages

logical effort

G gi

electrical effort

h CCoutin

branching effort

effort

f gh

F GBH

effort delay

DF f i

parasitic delay

P pi

delay

d f p

Con-path Coff-path
Con-path

Cout-path
Cin-path

B bi

D d i DF P

33

Method of Logical Effort

1)
2)
3)
4)
5)

Compute path effort

Estimate best number of stages
Sketch path with N stages
Estimate least delay
Determine best stage effort

6) Find gate sizes

34

F GBH
N log4 F
1
N

D NF P
f F N1

gi Couti
Cini
f

Limits of Logical Effort

Chicken and egg problem
Need path to compute G
But dont know number of stages without G

Simplistic delay model

Neglects input rise time effects

Interconnect
Iteration required in designs with wire

Maximum speed only

Not minimum area/power for constrained delay
35

Example 1
Calculate the
a) logical effort
b) parasitic delay
c) effort and
d) delay in the following 6-input AND implementations as a function of the path
electrical effort H. Which implementation is the fastest if a) H=1, b) H=5 and c)
H=20?

(a)

(b)

(c)

36

(d)

Example 2
For the path between x and F in the following
circuit calculate:
a. Total delay
b. Path effort and parasitic delay
c. minimum theoritical delay
6

20C
8

37

Summary
Logical effort is useful for thinking of delay in
circuits

Numeric logical effort characterizes gates

NANDs are faster than NORs in CMOS
Paths are fastest when effort delays are ~4
Path delay is weakly sensitive to stages, sizes
But using fewer stages doesnt mean faster paths
Delay of path is about log4F FO4 inverter delays
Inverters and NAND2 best for driving large caps

Provides language for discussing fast circuits

But requires practice to master
38