Lecture 3:

Nonideal
Transistor
Theory

Outline
Nonideal Transistor Behavior
High Field Effects
Mobility Degradation
Velocity Saturation
Channel Length Modulation
Threshold Voltage Effects
Body Effect
Drain-Induced Barrier Lowering
Short Channel Effect
Leakage
Subthreshold Leakage
Gate Leakage
Junction Leakage
Process and Environmental Variations
4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

Ideal Transistor I-V

Shockley long-channel transistor models

Vds
I ds Vgs Vt
2

Vgs Vt

4: Nonideal Transistor Theory

Vgs Vt
V V V
ds
ds
dsat

Vds Vdsat

CMOS VLSI Design 4th Ed.

cutoff
linear
saturation

Ideal vs. Simulated nMOS I-V Plot

65 nm IBM process, VDD = 1.0 V
Ids (A)
Simulated
Vgs = 1.0

Ideal
1200

Velocity saturation & Mobility degradation:

Ion lower than ideal model predicts

1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs
ds
DD
Saturation current increases
with Vds
Vgs = 1.0

800

Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with Vgs

400

Vgs = 0.8

Vgs = 0.6
200

Vgs = 0.6
Vgs = 0.4

Vds
0

0.2

4: Nonideal Transistor Theory

0.4

0.6

CMOS VLSI Design 4th Ed.

0.8

ON and OFF Current

Ion = Ids @ Vgs = Vds = VDD
Saturation

Ids (A)
1000
Ion = 747 mA @
Vgs = Vds = VDD
800

Vgs = 1.0

600
Vgs = 0.8
400
Vgs = 0.6
200
Vgs = 0.4
0

Vds
0

0.2

0.4

0.6

0.8

Ioff = Ids @ Vgs = 0, Vds = VDD

Cutoff

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

Electric Fields Effects

Vertical electric field: Evert = Vgs / tox
Attracts carriers into channel
Long channel: Qchannel Evert
Lateral electric field: Elat = Vds / L
Accelerates carriers from drain to source
Long channel: v = Elat

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

Coffee Cart Analogy

Tired student runs from VLSI lab to coffee cart
Freshmen are pouring out of the physics lecture hall
Vds is how long you have been up
Your velocity = fatigue mobility
Vgs is a wind blowing you against the glass (SiO2) wall
At high Vgs, you are buffeted against the wall
Mobility degradation
At high Vds, you scatter off freshmen, fall down, get up
Velocity saturation
Dont confuse this with the saturation region
4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

Mobility Degradation
High Evert effectively reduces mobility
Collisions with oxide interface
Essentially carrier mobility depends on Vgs and Vt

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

Velocity Saturation
At high Elat, carrier velocity rolls off
Carriers scatter off atoms in silicon lattice
Velocity reaches vsat
Electrons: 107 cm/s
Holes: 8 x 106 cm/s
Better model

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

Example 1
Calculate the effective carrier mobilities of nMOS
and pMOS transistors when fully ON. Assume Vgs =
1 V, Vt = 0.3 V and tox = 1.05 nm

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Example 2
Find the critical voltage for nMOS and pMOS
transistors that are fully ON, using the values
obtained in example 1 and L = 50nm.
(Hint Vc = EcL)
Which transistor is more vulnerable to velocity
saturation?

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

11

Vel Sat I-V Effects

Ideal transistor ON current increases with VDD2
2
W Vgs Vt

I ds Cox
Vgs Vt
L
2
2
2

Velocity-saturated ON current increases with VDD

I ds CoxW Vgs Vt vmax

Real transistors are partially velocity saturated

Approximate with a-power law model
Ids VDDa
1 < a < 2 determined empirically ( 1.3 for 65 nm)
4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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a-Power Model
0

I ds I dsat ds
Vdsat

I dsat

Vgs Vt

cutoff

Vds Vdsat

linear

Vds Vdsat

saturation

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

I dsat Pc

Vt

gs

Vdsat Pv Vgs Vt

a /2

13

Channel Length Modulation

Reverse-biased p-n junctions form a depletion region
Region between n and p with no carriers
Width of depletion Ld region grows with reverse bias
V
V
GND
Source
Gate
Drain
Leff = L Ld
Depletion Region
Width: L
Shorter Leff gives more current
Ids increases with Vds
n
n
L
+
+
L
Even in saturation
p GND bulk Si
DD

DD

eff

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Chan Length Mod I-V

I ds

gs

Vt 1 lVds
2

l = channel length modulation coefficient

not feature size
Empirically fit to I-V characteristics

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Threshold Voltage Effects

Vt is Vgs for which the channel starts to invert
Ideal models assumed Vt is constant
Really depends (weakly) on almost everything else:
Body voltage: Body Effect
Drain voltage: Drain-Induced Barrier Lowering
Channel length: Short Channel Effect

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Body Effect
Body is a fourth transistor terminal
Vsb affects the charge required to invert the channel
Increasing Vs or decreasing Vb increases Vt
Vt Vt 0 g

fs Vsb fs

fs = surface potential at threshold

fs 2vT ln

NA
ni

Depends on doping level NA

And intrinsic carrier concentration ni
g = body effect coefficient
g

tox

ox

2q si N A

4: Nonideal Transistor Theory

2q si N A
Cox

CMOS VLSI Design 4th Ed.

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Body Effect Cont.

For small source-to-body voltage, treat as linear

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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DIBL
Electric field from drain affects channel
More pronounced in small transistors where the
drain is closer to the channel
Drain-Induced Barrier Lowering
VVVh
Drain voltage also affect Vt
ttds

Vt Vt hVds
High drain voltage causes current to increase.

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Short Channel Effect

In small transistors, source/drain depletion regions
extend into the channel
Impacts the amount of charge required to invert
the channel
And thus makes Vt a function of channel length
Short channel effect: Vt increases with L
Some processes exhibit a reverse short channel
effect in which Vt decreases with L

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

20

Leakage
What about current in cutoff?
Simulated results
What differs?
Current doesnt
go to 0 in cutoff

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Leakage Sources
Subthreshold conduction
Transistors cant abruptly turn ON or OFF
Dominant source in contemporary transistors
Gate leakage
Tunneling through ultrathin gate dielectric
Junction leakage
Reverse-biased PN junction diode current

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Subthreshold Leakage
Subthreshold leakage exponential with Vgs
Vgs Vt 0 hVds kg Vsb

I ds I ds 0 e

nvT

Vds

1 e vT

n is process dependent
typically 1.3-1.7
Rewrite relative to Ioff on log scale

S 100 mV/decade @ room temperature

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

23

Gate Leakage
Carriers tunnel through very thin gate oxides
Exponentially sensitive to tox and VDD

A and B are tech constants

Greater for electrons
So nMOS gates leak more
Negligible for older processes (tox > 20 )
Critically important at 65 nm and below (tox 10.5 )
From [Song01]

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Junction Leakage
Reverse-biased p-n junctions have some leakage
Ordinary diode leakage
Band-to-band tunneling (BTBT)
Gate-induced drain leakage (GIDL)

p+

n+

n+

p+

p+

n+

n well
p substrate

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Diode Leakage
Reverse-biased p-n junctions have some leakage
VvD

T
I D I S e 1

At any significant negative diode voltage, ID = -Is

Is depends on doping levels
And area and perimeter of diffusion regions
Typically < 1 fA/m2 (negligible)

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

26

Band-to-Band Tunneling
Tunneling across heavily doped p-n junctions
Especially sidewall between drain & channel
when halo doping is used to increase Vt
Increases junction leakage to significant levels

Xj: sidewall junction depth

Eg: bandgap voltage
A, B: tech constants
4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Gate-Induced Drain Leakage

Occurs at overlap between gate and drain
Most pronounced when drain is at VDD, gate is at
a negative voltage
Thwarts efforts to reduce subthreshold leakage
using a negative gate voltage

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

28

Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces Vt
ION decreases with temperature
IOFF increases with temperature
I ds
increasing
temperature

Vgs

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

29

So What?
So what if transistors are not ideal?
They still behave like switches.
But these effects matter for
Supply voltage choice
Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Parameter Variation

fast

Transistors have uncertainty in parameters

Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values
Fast (F)
Leff: short
Vt: low
tox: thin
Slow (S): opposite
nMOS
Not all parameters are independent
for nMOS and pMOS

FF

pMOS

SF

TT

slow

slow

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

FS

SS

fast

31

Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: high
T: low
Corner

Voltage

Temperature

1.98

0C

1.8

70 C

1.62

125 C

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Process Corners
Process corners describe worst case variations
If a design works in all corners, it will probably
work for any variation.
Describe corner with four letters (T, F, S)
nMOS speed
pMOS speed
Voltage
Temperature

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Important Corners
Some critical simulation corners include

Purpose

nMOS

pMOS

VDD

Temp

Cycle time

Power

Subthreshold
leakage

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

34

Example 3
Consider an nMOS transistor manufactured in 65nm
process, with nominal threshold voltage equal to 0.3
V and doping levels of 8x10^17 cm^(-3). The
substrate is connected to ground with a contact.
What will be the change in the treshold voltage at
room temperature if the sourse is at 0.6V instead of
0V?
(Assume tox = 1.05 nm, q=1.6x10^(-19) Cb, vT =
kT/q = 26mV, ni = 1.45x10^10 cm^(-3), ox =
3.9x8.85x10^(-14) F/cm, Si = 11.7x8.85x10^(-14)
F/cm)
4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Example 4
An nMOS transistor has a threshold voltage of 0.4V and
Vdd = 1.2V. A designer considers reducing the threshold
voltage by 100 mV in order to increase transistor speed
(i) By how much would the saturation current increase
(for Vgs=Vds=Vdd) if the transistors were ideal?
(ii) By how much would the subthreshold leakage current
increase in room temperature for Vgs=0; Assume n=1.4
(iii) By how much would the subthreshold leakage current
increase at 120C?
Assume that Vt is constant.
k=1.3806504(24)1023 J/K

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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Example 5
Find the subthreshold leakage current of an inverter
at room temperature if the input A=0. Let n=2p =
1mA/V^2., n=1.4, and ABS(Vt)=0.4V. Assume the
body effect and DIBL coefficients are zero.

4: Nonideal Transistor Theory

CMOS VLSI Design 4th Ed.

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