This document discusses sequential logic and sequential circuits. It covers topics such as latches, edge-triggered flip-flops, timing methodologies for cascading flip-flops, asynchronous inputs and metastability, basic registers like shift registers, and timing specifications for sequential elements. Key concepts explained include feedback in sequential circuits, controlling feedback with clocks, the master-slave flip-flop structure for preventing race conditions, and timing constraints for proper operation of cascaded flip-flops.
This document discusses sequential logic and sequential circuits. It covers topics such as latches, edge-triggered flip-flops, timing methodologies for cascading flip-flops, asynchronous inputs and metastability, basic registers like shift registers, and timing specifications for sequential elements. Key concepts explained include feedback in sequential circuits, controlling feedback with clocks, the master-slave flip-flop structure for preventing race conditions, and timing constraints for proper operation of cascaded flip-flops.
This document discusses sequential logic and sequential circuits. It covers topics such as latches, edge-triggered flip-flops, timing methodologies for cascading flip-flops, asynchronous inputs and metastability, basic registers like shift registers, and timing specifications for sequential elements. Key concepts explained include feedback in sequential circuits, controlling feedback with clocks, the master-slave flip-flop structure for preventing race conditions, and timing constraints for proper operation of cascaded flip-flops.
This document discusses sequential logic and sequential circuits. It covers topics such as latches, edge-triggered flip-flops, timing methodologies for cascading flip-flops, asynchronous inputs and metastability, basic registers like shift registers, and timing specifications for sequential elements. Key concepts explained include feedback in sequential circuits, controlling feedback with clocks, the master-slave flip-flop structure for preventing race conditions, and timing constraints for proper operation of cascaded flip-flops.
Sequential Circuits Circuits with Feedback Outputs = f(inputs, past inputs, past outputs) Basis for building "memory" into logic circuits Door combination lock is an example of a sequential circuit State is memory State is an "output" and an "input" to combinational logic Combination storage elements are also memory new
How to control feedback? What stops values from cycling around endlessly
X1 X2
Xn
switching network
Z1 Z2
Zn
CS 150 - Fall 2000 - Sequential Logic - 3
Simplest Circuits with Feedback
Two inverters form a static memory cell Will hold value as long as it has power applied "1" "stored value"
"0"
How to get a new value into the memory cell?
Selectively break feedback path Load new value into cell
"remember"
"data"
"load"
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"stored value"
Memory with Cross-coupled Gates
Cross-coupled NOR gates Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) R
Q'
R S
Cross-coupled NAND gates
Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0) S' R'
S'
R' CS 150 - Fall 2000 - Sequential Logic - 5
Q'
Timing Behavior
Reset
Hold
Q'
Set
Reset
Set
R S Q \Q CS 150 - Fall 2000 - Sequential Logic - 6
100
Race
State Behavior of R-S latch
Truth table of R-S latch behavior Q Q' 0 1
S 0 0 1 1
R 0 1 0 1
Q hold 0 1 unstable
Q Q' 1 0
Q Q' 0 0
Q Q' 1 1
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Theoretical R-S Latch Behavior
SR=10 SR=00 SR=01
SR=01
Q Q' 0 1 SR=01
Q Q' 1 0 SR=10
SR=11
State Diagram States: possible values Transitions: changes based on inputs
SR=11
SR=01
possible oscillation between states 00 and 11
Q Q' 0 0
SR=11 SR=00 SR=11
SR=00
SR=10
Q Q' 1 1
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SR=00 SR=10
Observed R-S Latch Behavior
Very difficult to observe R-S latch in the 1-1 state One of R or S usually changes first
Ambiguously returns to state 0-1 or 1-0
A so-called "race condition" Or non-deterministic transition SR=10
SR=00 SR=01
SR=01
Q Q' 0 1 SR=01
Q Q' 1 0 SR=10
SR=11
SR=11
Q Q' 0 0
SR=11
SR=00
SR=00 CS 150 - Fall 2000 - Sequential Logic - 9
SR=00 SR=10
R-S Latch Analysis
Break feedback path R
Q(t) Q(t+)
S Q'
S S 0 0 0 0 1 1 1 1
R 0 0 1 1 0 0 1 1
Q(t) 0 1 0 1 0 1 0 1
Q(t+) 0 hold 1 0 reset 0 1 set 1 X not allowed X
Q(t)
R characteristic equation Q(t+) = S + R Q(t)
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Gated R-S Latch
Control when R and S inputs matter Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored Set
R'
enable' Q'
S'
100
S' R' enable' Q Q' CS 150 - Fall 2000 - Sequential Logic - 11
Reset
Clocks Used to keep time Wait long enough for inputs (R' and S') to settle Then allow to have effect on value stored
Clocks are regular periodic signals
Period (time between ticks) Duty-cycle (time clock is high between ticks - expressed as % of period) duty cycle (in this case, 50%)
period
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Clocks (contd) Controlling an R-S latch with a clock Can't let R and S change while clock is active (allowing R and S to pass) Only have half of clock period for signal changes to propagate Signals must be stable for the other half of clock period R'
clock' S'
Q' S stable changing stable changing stable R' and S' clock
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Cascading Latches Connect output of one latch to input of another How to stop changes from racing through chain? Need to control flow of data from one latch to the next Advance from one latch per clock period Worry about logic between latches (arrows) that is too fast
Q'
Q'
clock
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Master-Slave Structure Break flow by alternating clocks (like an air-lock) Use positive clock to latch inputs into one R-S latch Use negative clock to change outputs with another R-S latch
View pair as one basic unit
master-slave flip-flop twice as much logic output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops slave stage
master stage
Q'
P'
CLK CS 150 - Fall 2000 - Sequential Logic - 15
Q'
The 1s Catching Problem
In first R-S stage of master-slave FF 0-1-0 glitch on R or S while clock is high "caught" by master stage Leads to constraints on logic to be hazard-free slave stage
D Flip-Flop Make S and R complements of each other Eliminates 1s catching problem Can't just hold previous value (must have new value ready every clock period) Value of D just before clock goes low is what is stored in flipflop Can make R-S flip-flop by adding logic to make D = S + R' Q slave stage
Edge-Triggered Flip-Flops More efficient solution: only 6 gates sensitive to inputs only near edge of clock signal (not while high) D
holds D' when
clock goes low
negative edge-triggered D flip-flop (D-FF)
0 R
Clk=1 Q
4-5 gate delays
must respect setup and hold time constraints to successfully capture input
0 holds D when clock goes low D
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characteristic equation Q(t+1) = D
Edge-Triggered Flip-Flops (contd)
Step-by-step analysis D
D R
D R
Clk=0
Clk=0 S
S D
D when clock goes high-to-low data is latched
new D new D old D
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D when clock is low data is held
Edge-Triggered Flip-Flops (contd)
Positive edge-triggered Inputs sampled on rising edge; outputs change after rising edge
Negative edge-triggered flip-flops
Inputs sampled on falling edge; outputs change after falling edge 100 D CLK Qpos
positive edge-triggered FF
Qpos' Qneg
negative edge-triggered FF
Qneg'
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Timing Methodologies Rules for interconnecting components and clocks Guarantee proper operation of system when strictly followed
Approach depends on building blocks used for memory
elements Focus on systems with edge-triggered flip-flops Found in programmable logic devices
Many custom integrated circuits focus on level-sensitive latches
Basic rules for correct timing:
(1) Correct inputs, with respect to time, are provided to the flipflops (2) No flip-flop changes state more than once per clocking event
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Timing Methodologies (contd)
Definition of terms clock: periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level setup time: minimum time before the clocking event by which the input must be stable (Tsu) hold time: minimum time after the clocking event until which the input must remain stable (Th) Tsu Th
data
D Q
input clock
there is a timing "window"
around the clocking event during which the input must remain stable and unchanged in order to be recognized
clock stable changing data clock CS 150 - Fall 2000 - Sequential Logic - 22
D Q
Comparison of Latches and Flip-Flops
D Q CLK positive edge-triggered flip-flop
D CLK Qedge
D Q G
Qlatch
CLK transparent (level-sensitive) latch
behavior is the same unless input changes
while the clock is high CS 150 - Fall 2000 - Sequential Logic - 23
Comparison of Latches and Flip-Flops
(contd) Type
When inputs are sampled When output is valid
unclocked latch
always
propagation delay from input change
level-sensitive latch
clock high (Tsu/Th around falling edge of clock)
propagation delay from input change
or clock edge (whichever is later)
master-slave flip-flop
clock high (Tsu/Th around falling edge of clock)
propagation delay from falling edge
of clock
negative clock hi-to-lo transition propagation delay from falling edge edge-triggered (Tsu/Th around falling of clock flip-flop edge of clock)
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Typical Timing Specifications
Positive edge-triggered D flip-flop Setup and hold times Minimum clock width Propagation delays (low to high, high to low, max and typical) D
CLK
Tsu Th 20ns 5ns
Tsu 20ns
Th 5ns
Tw 25ns Tplh 25ns 13ns
Tphl 40ns 25ns
all measurements are made from the clocking event that is, the rising edge of the clock CS 150 - Fall 2000 - Sequential Logic - 25
Cascading Edge-triggered Flip-Flops
Shift register New value goes into first stage While previous value of first stage goes into second stage Consider setup/hold/propagation delays (prop must be > hold) IN
D Q
Q0
D Q
Q1
OUT
CLK
100 IN Q0 Q1 CLK
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Cascading Edge-triggered Flip-Flops
(contd) Why this works Propagation delays exceed hold times Clock width constraint exceeds setup time This guarantees following stage will latch current value before it changes to new value In Q0
Tsu 4ns
Tsu 4ns Tp 3ns
Q1
Tp 3ns
timing constraints guarantee proper operation of cascaded components
assumes infinitely fast
distribution of the clock
CLK Th 2ns
Th 2ns CS 150 - Fall 2000 - Sequential Logic - 27
Clock Skew The problem Correct behavior assumes next state of all storage elements determined by all storage elements at the same time tThis is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic Effect of skew on cascaded flip-flops: 100
In
CLK1 is a delayed version of CLK0
Q0 Q1 CLK0 CLK1
original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1 CS 150 - Fall 2000 - Sequential Logic - 28
Summary of Latches and Flip-Flops
Development of D-FF Level-sensitive used in custom integrated circuits can be made with 4 switches
Edge-triggered used in programmable logic devices
Good choice for data storage register
Historically J-K FF was popular but now never used
Similar to R-S but with 1-1 being used to toggle output (complement state) Good in days of TTL/SSI (more complex input function: D = JQ' + K'Q Not a good choice for PALs/PLAs as it requires 2 inputs Can always be implemented using D-FF
Preset and clear inputs are highly desirable on flip-flops
Used at start-up or to reset system to a known state CS 150 - Fall 2000 - Sequential Logic - 29
Metastability and Asynchronous inputs
Clocked synchronous circuits Inputs, state, and outputs sampled or changed in relation to a common reference signal (called the clock) E.g., master/slave, edge-triggered
Asynchronous circuits Inputs, state, and outputs sampled or changed independently of a common reference signal (glitches/hazards a major concern) E.g., R-S latch
Asynchronous inputs to synchronous circuits
Inputs can change at any time, will not meet setup/hold times Dangerous, synchronous inputs are greatly preferred Cannot be avoided (e.g., reset signal, memory wait, user input) CS 150 - Fall 2000 - Sequential Logic - 30
Synchronization Failure Occurs when FF input changes close to clock edge FF may enter a metastable state neither a logic 0 nor 1 May stay in this state an indefinite amount of time Is not likely in practice but has some probability logic 1
logic 0
logic 1
small, but non-zero probability
that the FF output will get stuck in an in-between state
logic 0 oscilloscope traces demonstrating synchronizer failure and eventual decay to steady state
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Dealing with Synchronization Failure
Probability of failure can never be reduced to 0, but it can be reduced (1) slow down the system clock: this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems (2) use fastest possible logic technology in the synchronizer: this makes for a very sharp "peak" upon which to balance (3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail)
asynchronous input
synchronized input
Q Clk
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synchronous system
Handling Asynchronous Inputs
Never allow asynchronous inputs to fan-out to more than one flip-flop Synchronize as soon as possible and then treat as synchronous signal Clocked Synchronous System Async Input
D Q
Synchronizer Q0
Async Input
D Q
D Q
Clock
Clock D Q
Q1
Clock
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Q0
D Q
Q1
Clock
Handling Asynchronous Inputs (contd)
What can go wrong? Input changes too close to clock edge (violating setup time constraint)
In
In is asynchronous and fans out to D0 and D1
Q0 Q1
one FF catches the
signal, one does not inconsistent state may be reached!
CLK
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Flip-Flop Features Reset (set state to 0) R
Synchronous: Dnew = R' Dold (when next clock edge arrives)
Asynchronous: doesn't wait for clock, quick but dangerous
Preset or set (set state to 1) S (or sometimes P)
Synchronous: Dnew = Dold + S (when next clock edge arrives)
Asynchronous: doesn't wait for clock, quick but dangerous
Both reset and preset
Dnew = R' Dold + S Dnew = R' Dold + R'S
(set-dominant) (reset-dominant)
Selective input capability (input enable/load) LD or EN
Multiplexer at input: Dnew = LD' Q + LD Dold
Load may/may not override reset/set (usually R/S have priority)
Complementary outputs Q and Q'
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Registers Collections of flip-flops with similar controls and logic Stored values somehow related (e.g., form binary value) Share clock, reset, and set lines Similar logic at each stage
Examples Shift registers Counters
OUT1
OUT2
OUT3
OUT4
"0" R S
R S
R S
R S
D Q
D Q
D Q
D Q
CLK
IN1
IN2
IN3
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IN4
Shift Register Holds samples of input Store last 4 input values in sequence 4-bit shift register: OUT1 IN
D Q
D Q
OUT2 D Q
CLK
CS 150 - Fall 2000 - Sequential Logic - 37
OUT3 D Q
OUT4
Universal Shift Register
Holds 4 values Serial or parallel inputs Serial or parallel outputs Permits shift left or right Shift in new values from left or right output
left_in left_out clear s0 s1
right_out right_in clock
input
clear sets the register contents
and output to 0 s1 and s0 determine the shift function s0 0 0 1 1
CS 150 - Fall 2000 - Sequential Logic - 38
s1 0 1 0 1
function hold state shift right shift left load new input
Design of Universal Shift Register
Consider one of the four flip-flops New value at next clock cycle: Nth cell to N-1th cell
to N+1th cell
Q D
clear 1 0 0 0 0
s0
0 0 1 1
s1
0 1 0 1
new value 0 output output value of FF to left (shift right) output value of FF to right (shift left) input
CLK
CLEAR s0 and s1 0 1 2 3 control mux Q[N-1] (left)
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Input[N]
Q[N+1] (right)
Shift Register Application
Parallel-to-serial conversion for serial transmission parallel outputs
parallel inputs
serial transmission
CS 150 - Fall 2000 - Sequential Logic - 40
Pattern Recognizer Combinational function of input samples In this case, recognizing the pattern 1001 on the single input signal OUT
OUT1 IN
D Q
D Q
OUT2 D Q
OUT3 D Q
CLK
CS 150 - Fall 2000 - Sequential Logic - 41
OUT4
Counters Sequences through a fixed set of patterns In this case, 1000, 0100, 0010, 0001 If one of the patterns is its initial state (by loading or set/reset) OUT1
IN
D Q
D Q
OUT2
D Q
OUT3
OUT4
D Q
CLK
Mobius (or Johnson) counter
In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 OUT1 IN
D Q
D Q
OUT2
D Q
CLK CS 150 - Fall 2000 - Sequential Logic - 42
OUT3
D Q
OUT4
Binary Counter Logic between registers (not just multiplexer) XOR decides when bit should be toggled Always for low-order bit, only when first bit is true for second bit, and so on OUT1 D Q
OUT2 D Q
OUT3 D Q
CLK
"1"
CS 150 - Fall 2000 - Sequential Logic - 43
OUT4 D Q
Four-bit Binary Synchronous Up-Counter
Standard component with many applications
Positive edge-triggered FFs w/ sync load and clear inputs
Parallel load data from D, C, B, A Enable inputs: must be asserted to enable counting RCO: ripple-carry out used for cascading counters high when counter is in its highest state 1111 implemented using an AND gate
