Architectures and Implementations of LDPC Decoding Algorithm
Architectures and Implementations of LDPC Decoding Algorithm
BER
Iterative
Code
1977 Convolutional Code 4.5dB 10
-3
Conv. Code
1993 Iterative Turbo Code 0.7dB Capacity
ML decoding
C. Berrou and A. Glavieux, "Near Optimum Error Correcting Coding And Decoding: Turbo- 4 dB
Codes," IEEE Trans. Comms., Vol.44, No.10, Oct 1996.
S. Chung; G.D. Forney, T.J. Richardson, and R. Urbanke, “On the design of low-density parity- 0 1 2 3 4 5 6
check codes within 0.0045 dB of the Shannon limit,” IEEE Communications Letters, vol.5,
(no.2), IEEE, Feb. 2001. pp.58-60.
SNR
LDPC Codes
Soft Decoding of LDPC Codes
Parallel vs. Serial Architectures
Platforms
Methods for Code Construction
VARIABLE
NODES
LDPC Codes
Soft Decoding of LDPC Codes
Parallel vs. Serial Architectures
Platforms
Methods for Code Construction
pn (1)
Qnm ln Rm 'n Rmn
pn (0) m ' ( n )
CHECK m
1 2 3
NODES
R
1n R 2n
m
n
R3
Qn
VARIABLE
NODE n
p (1)
Decoder input: ln n
pn (0)
1
Rmn Qn 'm Qnm sgn Qnm sgn(Qn 'm )
n 'N ( m) n ' ( m )
1
( x) log tanh( x) 1 ( x); x0
2
Q
R nm
3m
Q 1m
2m
Q
VARIABLE
1 2 n 3
NODE
b : Wordlength of messages
Engling Yeo University of California, Berkeley 8
Outline
LDPC Codes
Soft Decoding of LDPC Codes
Parallel vs. Serial Architectures
Platforms
Methods for Code Construction
LDPC Codes
Soft Decoding of LDPC Codes
Parallel vs. Serial Architectures
Platforms
Methods for Code Construction
Parallel architecture
Power and throughput efficiency
FPGA
Parallel adders and table lookups
Need to fit PEs and routing onto single FPGA
die
Existing implementations with serial
architecture limited to 56Mbps throughput
[M. M. Mansour and N. R. Shanbhag, “Memory-efficient turbo decoder architectures for LDPC
codes,” Proc. IEEE SIPS 2002, San Diego, CA, Oct. 2002.]
[T. Zhang and Keshab Parhi, “A 56Mbps (3,6)-Regular FPGA LDPC Decoder,” Proc. IEEE SIPS
2002, San Diego, CA, Oct. 2002.]
Custom ASIC
Parallel implementation demonstrated with 1Gbps
throughput
[A.J. Blanksby and C.J. Howland, “A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code
decoder,” IEEE Journal of Solid-State Circuits, vol.37, (no.3), (Proceedings of the IEEE 2001 Custom
Integrated Circuits Conference, San Diego, CA, USA, 6-9 May 2001.) IEEE, March 2002. p.404-12. ]
Routing congestion
Logic density is 50%
Design not scalable to codes with larger block
sizes
LDPC Codes
Soft Decoding of LDPC Codes
Parallel vs. Serial Architectures
Platforms
Methods for Code Construction
Algebraic Constructions
Cyclic or quasi-cyclic properties
Use of shift registers
Parallel implementation has to address sparse code /
interconnect issue.
Engling Yeo University of California, Berkeley 19
Summary
STALL!!
Butterfly
Unit Unit
Memory
Memory
Memory
Memory
Memory
Memory