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The Processor

The document describes the basic components and operation of a central processing unit (CPU). It discusses how the CPU fetches instructions from memory and uses components like registers, arithmetic logic units (ALUs), and multiplexers to execute instructions. It also covers different types of instructions like register-format, load/store, and branch instructions. The CPU uses a main control unit to derive control signals from instructions and coordinate the datapath to execute each instruction type in the appropriate manner.

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PradhibaSelvarani
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34 views

The Processor

The document describes the basic components and operation of a central processing unit (CPU). It discusses how the CPU fetches instructions from memory and uses components like registers, arithmetic logic units (ALUs), and multiplexers to execute instructions. It also covers different types of instructions like register-format, load/store, and branch instructions. The CPU uses a main control unit to derive control signals from instructions and coordinate the datapath to execute each instruction type in the appropriate manner.

Uploaded by

PradhibaSelvarani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Instruction Execution

PC instruction memory, fetch instruction


Register numbers register file, read registers
Depending on instruction class
Use ALU to calculate
Arithmetic result
Memory address for load/store
Branch target address
Access data memory for load/store
PC target address or PC + 4
CPU Overview
Multiplexers
Cant just join
wires together
Use multiplexers
Control
Logic Design Basics

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Information encoded in binary
Low voltage = 0, High voltage = 1
One wire per bit
Multi-bit data encoded on multi-wire buses
Combinational element
Operate on data
Output is a function of input
State (sequential) elements
Store information
Combinational Elements
AND-gate
Y = A & B
A
B
Y
I0
I1
Y
M
u
x
S
Multiplexer
Y = S ? I1 : I0
A
B
Y
+
A
B
Y
ALU
F
Adder
Y = A + B
Arithmetic/Logic Unit
Y = F(A, B)
Sequential Elements
Register: stores data in a circuit
Uses a clock signal to determine when to
update the stored value
Edge-triggered: update when Clk changes
from 0 to 1
D
Clk
Q
Clk
D
Q
Sequential Elements
Register with write control
Only updates on clock edge when write
control input is 1
Used when stored value is required later
D
Clk
Q
Write
Write
D
Q
Clk
Clocking Methodology
Combinational logic transforms data during
clock cycles
Between clock edges
Input from state elements, output to state
element
Longest delay determines clock period
Building a Datapath
Datapath
Elements that process data and addresses
in the CPU
Registers, ALUs, muxs, memories,
We will build a MIPS datapath
incrementally
Refining the overview design

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Instruction Fetch
32-bit
register
Increment by
4 for next
instruction
R-Format Instructions
Read two register operands
Perform arithmetic/logical operation
Write register result
Load/Store Instructions
Read register operands
Calculate address using 16-bit offset
Use ALU, but sign-extend offset
Load: Read memory and update register
Store: Write register value to memory
Branch Instructions
Read register operands
Compare operands
Use ALU, subtract and check Zero output
Calculate target address
Sign-extend displacement
Shift left 2 places (word displacement)
Add to PC + 4
Already calculated by instruction fetch
Branch Instructions
Just
re-routes
wires
Sign-bit wire
replicated
Composing the Elements
First-cut data path does an instruction in
one clock cycle
Each datapath element can only do one
function at a time
Hence, we need separate instruction and data
memories
Use multiplexers where alternate data
sources are used for different instructions
R-Type/Load/Store Datapath
Full Datapath
ALU Control
ALU used for
Load/Store: F = add
Branch: F = subtract
R-type: F depends on funct field

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ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract
0111 set-on-less-than
1100 NOR
ALU Control
Assume 2-bit ALUOp derived from opcode
Combinational logic derives ALU control
opcode ALUOp Operation funct ALU function ALU control
lw 00 load word XXXXXX add 0010
sw 00 store word XXXXXX add 0010
beq 01 branch equal XXXXXX subtract 0110
R-type 10 add 100000 add 0010
subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
set-on-less-than 101010 set-on-less-than 0111
The Main Control Unit
Control signals derived from instruction
0 rs rt rd shamt funct
31:26 5:0 25:21 20:16 15:11 10:6
35 or 43 rs rt address
31:26 25:21 20:16 15:0
4 rs rt address
31:26 25:21 20:16 15:0
R-type
Load/
Store
Branch
opcode always
read
read,
except
for load
write for
R-type
and load
sign-extend
and add
Datapath With Control
R-Type Instruction
Load Instruction
Branch-on-Equal Instruction
Implementing Jumps
Jump uses word address
Update PC with concatenation of
Top 4 bits of old PC
26-bit jump address
00
Need an extra control signal decoded from
opcode
2 address
31:26 25:0
Jump
Datapath With Jumps Added

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