Courtesy RK Brayton (UCB)

and A Kuehlmann (Cadence)

1
Logic Synthesis

Timing Analysis


2
Timing Analysis - Delay Models
Simple model 1:
A
k
= arrival time = max(A
1
,A
2
,A
3
) + D
k

D
k
is the delay at node k, parameterized according to function f
k
and
fanout node k

Simple model 2:
D
k

A1
A2
A3
Ak
A1
A2
A3
Ak
0
A1 A2
A3
Ak
D
k1
D
k2
D
k3
Can also have different times for rise time and fall time

A
k
= max{A
1
+D
k1
,
A
2
+D
k2
,A
3
+D
k3
}
3
Static delay analysis
// level of PI nodes initialized to 0,
// the others are set to -1.
// Invoke LEVEL from PO
Algorithm LEVEL(k) { // levelize nodes
if( k.level != -1)
return(k.level)
else
k.level = 1+max{LEVEL(k
i
)|k
i
fanin(k)}
return(k.level)
}

// Compute arrival times:
// Given arrival times on PIs
Algorithm ARRIVAL() {
for L = 0 to MAXLEVEL
for {k|k.level = L}
A
k
= MAX{A
ki
} + D
k
}
4
Required Times
Required times:

given required times on primary outputs

Traverse in reverse topological order (i.e. from primary outputs
to primary inputs)
if (k
i
, k ) is an edge between k
i
and k, R
k
i
,k
= R
k
- D
k
(this is the edge required time)
Hence, the required time of output of node k is
R
k
= min ( R
k,k
j

| k
j
fanout(k) )
k
k
i
j
S
ki
S
k S
j
k
i
5
Propagating Slacks
Slacks: slack at the output node k is S
k
= R
k
-A
k
Since R
ki
,
k
=R
k
-D
k

S
ki
,
k
=R
ki
,
k
- A
ki

S
ki
,
k
+ A
ki
= R
k
-D
k
= S
k
+ A
k
- D
k
Since A
k
= max {A
kj
} + D
k
S
ki
,
k
= S
k
+ max {A
kj
} - A
ki
k
j
, k
i
fanin (k )
S
ki
= min{S
ki
,
j
} j fanout (k
i
)

Notes:
Each edge is the graph has a slack and a required time
Negative slack is bad.
k
k
i
j
S
ki
S
k S
j
k
i
6
Sequential networks

Arrival times known at l
1
and l
2

Required times known at l
3
, l
4
, and l
5

Delay analysis gives arrival and required times (hence slacks)
for C
1
, C
2
, C
3
, C
4

C3
C1
C2
C4
l1
l2 l3
l4
l5
7
Static critical paths
Min-Max problem: minimize max{-S
i
, 0}

A static critical path of a Boolean network is a path P = {i
1
,i
2
,,i
p
}
where S
i
k
,
i
k+1
< 0

Note: if a node k is on a static critical path, then at least one of the
fanin edges of k is critical. Hence, all critical paths reach from an
input to an output.
Note: There may be several critical paths
8
Example: Static critical paths
2 1
2 2 1
2 1
R2=5 R1=5
A8=0
A9=0
9
8
0
0
1
0
-1
-1
-1
-1
1
0
-1
-1
5
7 6
3
1
2
4
A1=6 R1=5
A2=5 R2=5

S
1
=-1 R3=3
S
2
=0 R7=1
S
3,1
=-1 R9=-1
S
4,1
= -1
S
4,2
= 0
S
5,2
= 1
S
6,3
= 0
S
7,3
= -1
S
7,4
= -1
S
7,5
= 1
S
8,6
= 0
S
9,7
= -1

critical path edges
S
ki
,
k
= S
k
+ max{A
kj
} - A
ki
, k
j
,k
i
fanin(k)
S
k
= min{S
k
,
kj
}, k
j
fanout(k)
1
4
2
3 4
5 6
9
Timing analysis problems
We want to determine the true critical paths of a circuit in order to:
determine the minimum cycle time that the circuit will function
identify critical paths from performance optimization - dont want to
try to optimize the wrong (non-critical) paths
Implications:
Dont want false paths (produced by static delay analysis)
Delay model is worst case model. Need to ensure correctness for
case where i
th
gate delay D
i
M
10
Functional Timing Analysis
What is Timing Analysis?
Estimate when the output of a given circuit gets stable
clock
Combinational
block
0
0
T
0
11
Why Timing Analysis?
Timing verification
Verifies whether a design meets a given timing constraint
Example: cycle-time constraint
Timing optimization
Needs to identify critical portion of a design for further
optimization
Critical path identification
In both applications, the more accurate, the better
12
Timing Analysis - Basics
Nave approach - Simulate all input vectors with SPICE
Accurate, but too expensive
Gate-level timing analysis
Focus of this lecture
Less accurate than SPICE due to the level of abstraction,
but much more efficient
Scenario:
Gate/wire delays are pre-characterized (accuracy loss)
Perform timing analysis of a gate-level circuit assuming
the gate/wire delays

Gate-level Timing Analysis
A naive approach is topological analysis
Easy longest-path problem
Linear in the size of a network
Not all paths can propagate signal events
False paths
If all longest paths are false,
topological analysis gives delay
overestimate
Functional timing analysis = false-path-
aware timing analysis
Compute false-path-aware arrival time
arr(x
1
)=0 arr(x
2
)=0
False
path
aware
arr(z)?
z
x
1
x
2
1
1
Example: 2-bit Carry-skip Adder
c_in
a0
b0
a1
b1
s0
s1
c_out
mux
Length 5
Length 1
ripple carry adder
1
0
15
False Path Analysis - Basics
Is a path responsible for delay?
If the answer is no, can ignore the path for delay computation
Check the falsity of long paths until we find the longest true path
How can we determine whether a path is false?

Delay underestimation is unacceptable
Can lead to overlooking a timing violation
Delay overestimation is not desirable, but acceptable
Topological analysis can give overestimate, but never give
underestimate
16
Controlling/Non-Controlling Values
0
0
1
Controlling value of AND
Controlled value of AND
1 1
Controlling value of OR
Controlled value of OR
Non-Controlling value of AND
0
Non-Controlling value of OR
1
1
0
17
Static Sensitization
A path is statically-sensitizable if there exists an input vector such
that all the side inputs to the path are set to non-controlling
values
This is independent of gate delays

1
0
Controlling value!
These paths are not
statically-sensitizable
The longest true path
is of length 2?
t=0
t=0
t=0
1
0
18
Static Sensitization
The (dashed) path is responsible for delay!
Delay underestimation by static sensitization (delay = 2 when
true delay = 3)
incorrect condition
0
0
1
2
1
2 3
0
19
What is Wrong with Static Sensitization?
The idea of forcing non-controlling values to side inputs
is okay, but timing was ignored
The same signal can have a controlling value at one time
and a non-controlling value at another time.


How about timing simulation as a correct method?
20
Timing Simulation
2
1
4
1
1
0
0
2
1
4
2 3
Implies that delay = 0 for these inputs
BUT!
0
4
21
2
1
4->2
1
1
Timing Simulation
0
0
2
2
1
2 3
3 4
Implies that delay = 4 with the same set of
inputs.
2
22
What is Wrong with Timing Simulation?
If gate delays are reduced, delay estimates can
increase

Not acceptable since
Gate delays are just upper-bounds, actual delay is in [0,d]
Delay uncertainty due to manufacturing
We are implicitly analyzing a family of circuits where gate
delays are within the upper-bounds
23
Monotone Speedup Property
Definition: For any circuit C, if
C is obtained from C by reducing some gate delays, and
delay_estimate(C) delay_estimate(C),
then delay_estimate has Monotone Speedup property

Timing simulation does not have this property

24
Timing Simulation Revisited
2
1
4
1
1
0
0
2
1
4
3
4
4
means that the rising signal
occurs anywhere between
t = -infinity and t = 4.
X-valued simulation
4
0
Timing Simulation Revisited
Timed 3-valued (0,1,X) simulation
called X-valued simulation
Monotone speedup property is satisfied.

Underlying model of
floating mode condition [Chen, Du]
Applies to simple gate networks only
viability [McGeer, Brayton]
Applies to general Boolean networks

False Path Analysis Algorithms
Checking the falsity of every path explicitly is too expensive - exponential # of
paths
State-of-the-art approach:
1. Start: set L = L
top
-

! = topological longest path delay -

!
L
old
= 0
2. Binary search:
If (Delay(L))
(
*
)
! L = |L-L
old
|/2, L
old
= L, L = L + ! L
Else, ! L = |L-L
old
|/2, L
old
= L, L = L - ! L
If (L > L
top
or ! L < threshold), L = L
old
, done

(
*
)
Delay(L) = 1 if there an input vector under which an output gets stable only at time t
where L t ?
Can be reduced to
a SAT problem [McGeer, Saldanha, Brayton, ASV] or
a timed-ATPG [Devadas, Keutzer, Malik]

27
SAT-based False Path Analysis
Decision problem:
Is there an input vector under which the output gets stable only after t = T ?
Idea:
1. characterize the set of all input vectors S(T) that make the output
stable no later than t = T
2. check if S(T) contains S = all possible input vectors
This check is solved as a SAT problem:
Is S \ S(T) empty? - set difference + emptiness check
Let F and F(T) be the characteristic functions of S and S(T)
Is F !F(T) satisfiable?
28
Example
Assume all the PIs arrive at t = 0, all gate delays = 1
Is the output stable time t > 2?

a
b
c
d
e
f
g
29
Example
g(1,t=2) : the set of input vectors under which
g gets stable to value = 1 no later than t =2

a
b
c
d
e
f
g
g(1,t=2) = d(1,t=1) f(1,t=1)
g(1,t=) = onset = !a!bc = g(1,t=2) = S
1
Onset:
stabilized by t=2?
= (a(0,t=0) b(0,t=0)) (c(1,t=0) e(1,t=0))
= !a!b(c ) = !a!bc = S
1
(t=2)
30
Example
g(0,t=2) : the set of input vectors under which
g gets stable to value = 0 no later than t=2

a
b
c
d
e
f
g
g(0,t=2) = d(0,t=1) f(0,t=1)
= (a(1,t=0) b(1,t=0)) (c(0,t=0) e(0,t=0))
= (a+b) + (!c ) = a+b = S
0
(t=2)
g(0,t=) = offset = a+b+!c = S
0
31
Example
g(0,t=2) : the set of input vectors under which
g gets stable to 0 no later than t=2

a
b
c
d
e
f
g
g(0,t=2) = a+b
g(0,t=) = offset = a+b+!c
Offset:
NOTstabilized by t=2
under abc=000
g(0,t=) \ g(0,t=2) = (a+b+!c) !(a+b) = !a !b !c = satisfiable
32
Summary
False-path-aware arrival time analysis is well-
understood
Practical algorithms exist
Can handle industrial circuits easily
Remaining problems
Incremental analysis (make it so that a small change in the
circuit does not make the analysis start all over)
Integration with logic optimization
DSM issues such as cross-talk-aware false path analysis
33
Timed ATPG
Yet another way to solve the same decision problem

A generalization of regular ATPG:
regular ATPG
find an input vector that differentiates a fault-free circuit and a
faulty circuit in terms of functionality
Timed ATPG
find an input vector that exhibits a given timed behavior
Timed extension of PODEM