Homework solutions

EE3143
Resistive circuits
Problem 1
Use KVL and Ohms law to compute voltages v
a
and v
b
.
+
+
+
+
v
2
-
- -
-
v
1
From Ohms law:
v
1
=8kO-i
1
=8[V]

v
2
=2kO-i
2
=-2[V]

Form KVL:
v
a
=5[V]-v
2
=7[V]
v
b
=15[V]-v
1
-v
a
=0[V]

Resistive circuits
Problem 2
Write equations to compute voltages v
1
and v
2
, next find the current value of i
1

From KCL:
50 mA=v
1
/40+(v
1
-v
2
)/40
and
100 mA=v
2
/80+(v
2
-v
1
)/40

Multiply first equation by 40:
2=v
1
+v
1
-v
2
=2v
1
-v
2

From second equation:
8=v
2
+2(v
2
-v
1
)=3v
2
-2v
1
add both sides:

10=2v
2
=> v
2
=5 [V], v
1
=1+v
2
/2=3.5[V]
i
1
= (v
1
-v
2
)/40=-1.5/40=37.5 [mA]



50 mA
O 40
O 40 O 80
100 mA
i
1
i
1
v
2
v
1
Thevenin & Norton
Problem 3: Find Thevenin and Norton equivalent circuit for the network shown.
I
1

N
2

I
2

v
t

N
1

From KVL
Thevenin & Norton
I
1

N
2

I
2

I
sc

N
1

From KVL
Thevenin & Norton

Note: Negative v
t
indicates that the polarity is reversed and
as a result this circuit has a negative resistance.

+
_
V
t
=-6 V

R
Th
=-1.33

A
B
Thevenin Equivalent
I
n
=4.5 A

R
Th
=-1.33

A
B
Norton Equivalent
R
Th
=v
t
/I
sc
=-1.33

Problem 4: Find the current i and the voltage v across LED diode
in the circuit shown on Fig. a) assuming that the diode
characteristic is shown on Fig. b).
Draw load line. Intersection of load
line and diode characteristic is the i
and v across LED diode: v 1.02 V
and i 7.5 mA.
Problem 5: Sketch i versus v to scale for each of the circuits
shown below. Assume that the diodes are ideal and allow v to
range from -10 V to +10 V.
-10 -5 0 5 10
0
1
2
3
4
5
v (V)
i

(
m
A
)
(a)
Diode is on for v > 0 and R=2k.
+


v


_
2k
i
In a series connection voltages are added for each constant current
Problem 5: Sketch i versus v to scale for each of the circuits
shown below. Assume that the diodes are ideal and allow v to
range from -10 V to +10 V.
-10 -5 0 5 10
0
1
2
3
4
5
v (V)
i

(
m
A
)
(b)
Due to the presence of the 5V
supply the diode conducts only
for v > 5, R = 1k
+


v


_
1k
i
+

_
5V
First combine diode and resistance then add the voltage source
(c)
-10 -5 0 5 10
-5
0
5
10
v (V)
i

(
m
A
)
Diode B is on for v > 0 and R=1k.
Diode A is on for v < 0 and R=2k.
+




v



_
2k
i
1k
A B
Problem 5: Sketch i versus v to scale for each of the circuits
shown below. Assume that the diodes are ideal and allow v to
range from -10 V to +10 V.
(d)
-10 -5 0 5 10
-5
0
5
10
v (V)
i

(
m
A
)
Diode D is on for v > 0 and R=1k.
Diode C is on for v < 0 and R=0.
+




v


_
i
1k
C
D
Problem 5: Sketch i versus v to scale for each of the circuits
shown below. Assume that the diodes are ideal and allow v to
range from -10 V to +10 V.
Problem 6
Sketch the transfer characteristic (v
o
versus v
in
) for the circuit shown in the
figure below. Assume that the diode is ideal.
Modeling a piecewise characteristic of a device
1k
i
v
i
- + v
v
x
In a parallel connection currents are added for each constant voltage
Problem 6
Sketch the transfer characteristic (v
o
versus v
in
) for the circuit shown in the
figure below. Assume that the diode is ideal.
Modeling a piecewise characteristic of a device
1k
i
v
i
- + v
v
x
In a parallel connection currents are added for each constant voltage
Problem 6
Add the voltage source.
Modeling a piecewise characteristic of a device
1k
i
- + v
In a series connection voltages are added for each constant current
+



v
o


_
+
V
in
-
v
i
v
in
Problem 6
Add the voltage source.
Modeling a piecewise characteristic of a device
1k
i
- + v
+



v
o


_
+
V
in
-
2k
In a parallel connection currents are added for each constant voltage
v
i
v
in
Problem 6
Add the voltage source.
Modeling a piecewise characteristic of a device
1k
i
- + v
+



v
o


_
+
V
in
-
2k
In a parallel connection currents are added for each constant voltage
v
i
v
in
I
a
4V
-
+
5V
-
+
(a)
S
D
G
I
b

1V
-
+
3V
-
+
(b)
D
S
G
I
c

4V
+
-
5V
-
+
(c)
G
D
S
I
d

3V
-
+
1V
-
+
(d)
G
S
D
1.8 M 2 k
0.2 M
sin(200t)
+
_
Z
in

+20 V
D
G
S
Loop 1
Problem 8: Consider the amplifier shown below.
a) Find v
GS
(t). Assume that the coupling capacitor is a short circuit
for the ac signal and an open circuit for the dc.
Soln (a): In loop 1 the 1.8
M and 200 k resistors
act as voltage divider.
The voltage drop across
200 k resistor is the dc
voltage V
GSQ

V
GSQ
= 20*0.2/2=2 V
Treating the capacitor as short for ac signals, we have
V
GS
=2 + sin(200t)
b) If the FET has V
t0
= 1V and K = 0.5 mA/V
2
, sketch its
drain characteristics to scale for V
GS
= 1, 2, 3, and 4 V.
c) Draw the load line for the amplifier on the
characteristics.
d) Find the values of V
DSQ
, V
DSmin
, and V
DSmax
.
To obtain the drain characteristics apply the following
equations
0 5 10 15 20
0
1
2
3
4
5
V
GS
= 1V
V
GS
= 2V
V
GS
= 3V
V
GS
= 4V
Load Line
Drain Characteristics
V
DS
(V)
i
D

(
m
A
)
b) Plot shows the drain characteristics for V
GS
= 1, 2, 3, and 4 V.
c) To get the load line apply KVL to loop 2:
20 2 k*i
D
(t) = V
DS
(t)
The red line in the plot is the load line.
1.8 M 2 k
0.2 M
sin(200t)
+
_
Z
in

+20 V
D
G
S
Loop 2
0 5 10 15 20
0
1
2
3
4
5
V
GS
= 1V
V
GS
= 2V
V
GS
= 3V
V
GS
= 4V
Load Line
Drain Characteristics
V
DS
(V)
i
D

(
m
A
)
d) V
DSQ
, V
DSmin
, and V
DSmax

are the points at which the
load line intersects the
drain characteristics for V
GS

= 2 V, 3 V and 1 V
respectively.
V
DSQ
= 19 V
V
DSmin
= 16 V
V
DSmax
= 20 V
d) Find the values of V
DSQ
, V
DSmin
, and V
DSmax
.
R
1
=
72 k
R
2
=
28 k
+

v
in


_
C
1

+10 V
C
2

R
L
=
1 k
+


v
o

_
R
D
= 5 k
The 72 k and 28 k
resistors act as a voltage
divider. The voltage drop
across 28 k resistor is the dc
voltage V
GSQ
is equal to



Problem 9: Consider the common source amplifier shown below. Assume
NMOS transistor has the following parameters:
=60
2
, =5 , =100 ,

=, and

=1.5 .

a) Find the values of

and

V
R R
R
V
DD GSG
8 . 2
28 72
28
10 V
2 1
2
=
+
=
+
=
2
/ 6 . 0
2
1
K V mA
L
W
KP =
|
.
|

\
|
=
( ) mA V V K I
to GSQ DQ
014 . 1
2
= =
( ) V I R V V
DQ D DD DSQ
93 . 4 = =
mS KI g
DQ m
56 . 1 2 = =
Problem 9 b): - Assuming that the coupling capacitors are short circuits
for the ac signal, determine the following: voltage gain, input
resistance and output resistance.
O =
+
= 3 . 833
1 1
1
'
L D
L
R R
R
O =
+
= k
R R
R
in
16 . 20
1 1
1
2 1
O = = k R R
D o
5
3 . 1
'
= =
L m v
R g A
R
1
=
72 k
R
2
=
28 k
+

v
in


_
C
1

+10 V
C
2

R
L
=
1 k
+


v
o

_
R
D
= 5 k
R
1

R
2

v(t)
+
_
C
1

+15 V
R
S
=
0.5 k
C
2

R
L
=
5 k
R
+



v
in
(t)



_
+


v
o

_
R
D
=
2 k
R
in

Problem 10: - Consider the common source amplifier shown below.
Assume NMOS transistor has the following parameters:
=75
2
, =10 , =400 ,

=, and

=1 .
a) If R
in
= 250 k, find the values for R
1
and R
2
to achieve

=2 .
R
1

R
2

v(t)
+
_
C
1

+15 V
R
S
=
0.5 k
C
2

R
L
=
5 k
R
+



v
in
(t)



_
+


v
o

_
R
D
=
2 k
R
in

We have:
Given:





Solve for R
1
:
2
/ 5 . 1
2
1
K V mA
L
W
KP =
|
.
|

\
|
=
( ) mA V V K I
to GSQ DQ
2
2
= =
V K I V V
DQ to GSQ
155 . 2 = + =
V I R V
DQ S S
1 = =
V V V V
S GSQ G
155 . 3 = + =
in DD DD G
R
R
V
R R
R
V V
1 2 1
2
1
=
+
=
O = = = M R
V
V R
in
G
DD
19 . 1 10 * 250 *
155 . 3
1
* 15
1
3
1
We have R
in
= 250 k and R
1
= 1.19 M


Solve for R
2
:

b) Determine the voltage gain
( )
2 1
2 1
2 1
*
||
R R
R R
R R R
in
+
= =
O =
+
= k R
R M
R M
k 5 . 316
19 . 1
* 19 . 1
250
2
2
2
O =
+ +
= 54 . 454
1 1 1
1
'
S L d
L
R R R
R
mS KI g
DQ m
46 . 3 2 = =
572 . 1
'
0
= = =
L m
in
v
R g
v
v
A
Problem BJT P1: It has been found that in the circuit below V
E
= 1V.
If V
BE
= -0.6V, determine: V
B
, I
B
, I
E
, I
C
, , and .
V
E
= 1V
I
E
I
C
I
B
V
BE
= -0.6V
V
B

Soln (a): From KVL:


From KVL:
Ohms law:

V R
E
1 * I 5V
E
+ =
5000 * I 4V
E
= mA 8 . 0 I
E
=
V V V V
EB E B
4 . 0 6 . 0 1 = = =
B B B
R I V * =
O = k I
B
20 * 0.4V A I
B
20 =
mA I I I
B E C
78 . 0 = =
39 = =
B
C
I
I
|
975 . 0 = =
E
C
I
I
o
Problem BJT P2: - For the circuit below assume both transistors are
silicon-based with = 100. Determine: a) I
C1
, V
C1
,
V
CE1
. b) I
C2
, V
C2
, V
CE2
.

R
B1
I
B1
V
BE1
I
C1
+ I
B2
I
C2
V
BE2
R
C1
R
C2
R
E2
I
E2
V
C1
V
CE1
V
CE2
I
C1
I
B2
Soln:
Assume V
BE
= V
BE1
=V
BE2
= 0.7V

Part (a): - Apply KVL along the path
(red line).

0 * 30
1 1 1
= + +
BE B B
V R I
A I
B
07 . 39
10 * 750
7 . 0 30
3
1
=

=
mA I I
B C
907 . 3 *
1 1
= = |
R
B1
I
B1
V
BE1
I
C1
+ I
B2
I
C2
V
BE2
R
C1
R
C2
R
E2
I
E2
V
C1
V
CE1
V
CE2
I
C1
I
B2
Part (a) contd.: - Apply KVL along the path (red line).

We know that

substituting we get


( ) 0 30
2 2 2 1 2 1
= +
E E BE C B C
R I V R I I
( )
B E
I I 1 + = |
( ) 0 1 7 . 0 2234 . 24 30
2 2 1 2
= +
E B C B
R I R I |
( ) 0 * 101 0766 . 5
2 1 2
= +
E C B
R R I A I
B
559 . 10
2
=
( )
1 2 1 1
* 30
C B C C
R I I V + =
( )
] [ 7111 . 5
2 . 6 * 010559 . 0 907 . 3 30
1
V
V
C
=
+ =
V V V
C CE
7111 . 5
1 1
= =
R
B1
I
B1
V
BE1
I
C1
+ I
B2
I
C2
V
BE2
R
C1
R
C2
R
E2
I
E2
V
C1
V
CE1
V
CE2
V
C2
V
E2
I
C1
I
B2
Part (b): - Apply KVL along the path (red line).









mA A I I
B E
0662 . 1 559 . 10 * 101 ) 1 (
2 2
= = + = |
mA I I
B C
0556 . 1
2 2
= = |
2 2 2
30
C C C
R I V =
V V
C
888 . 8 20 * 0556 . 1 30
2
= =
V R I V
E E E
0111 . 5
2 2 2
= =
V V V V
E C CE
8769 . 3
2 2 2
= =
Problem BJT P3: - Design the bias circuit (find R
C
and R
B
) to give a Q-
point of I
C
= 20A and V
CE
= 0.9V if the transistor current gain
F
= 50
and V
BE
= 0.65V.
What is the Q-point if the current gain of the transistor is 125?

I
C
= 20A

I
B
V
CE
= 0.9V

V
BE
= 0.65V

Soln: Apply KVL along the path (red line).









( ) 5 . 1 = + +
CE C B C
V R I I
5 . 1 9 . 0 = +
|
|
.
|

\
|
+
C
C
C
R
I
I
|
6 . 0
1
1 =
|
|
.
|

\
|
+
C C
R I
|
6 . 0
50
1
1 10 * 20
6
=
|
.
|

\
|
+

C
R
O = =

k R
C
4117 . 29
10 * 4 . 20
6 . 0
6
I
C
= 20A

I
B
V
CE
= 0.9V

V
BE
= 0.65V

Soln contd.: (find R
C
and R
B
) to give a Q-point of
I
C
= 20A and V
CE
= 0.9V.
Apply KVL along the path (red line).








( ) 5 . 1 = + + +
BE B B C B C
V R I R I I
5 . 1 65 . 0 = + +
|
|
.
|

\
|
+
B
C
C
C
C
R
I
R
I
I
| |
5 . 1 65 . 0
50
10 * 20
6 . 0
6
= +
|
|
.
|

\
|
+

B
R
25 . 0 * 10 * 4 . 0
6
=

B
R
O = =

k R
B
625
10 * 4 . 0
25 . 0
6
I
C
I
B
V
CE
V
BE
= 0.65V

I
C
+ I
B
Soln contd.: Find the Q-point if the current gain,
F
= 125.
We have R
C
=29.41k, and R
B
=625k, from previous
calculations.
Apply KVL along the path (red line).








( ) 5 . 1 = + + +
BE B B C B C
V R I R I I
( ) 85 . 0 625 * 41 . 29 = + + k I k I I
B B B
|
( ) 85 . 0 625 41 . 29 * 126 = +
B
I k k
A I
B
196 . 0
10 * 331 . 4
85 . 0
6
= =
A I I
B C
| 53 . 24 10 * 196 . 0 * 125
6
= = =

I
C
I
B
V
CE
V
BE
= 0.65V

I
C
+ I
B
Soln contd.: Apply KVL along the path
(red line).





The Q-Point is:


( ) 5 . 1 = + +
CE C B C
V R I I
( ) 5 . 1 41 . 29 * 10 * 196 . 0 53 . 24
6
= + +

CE
V k
V V
CE
773 . 0 727 . 0 5 . 1 = =
( ) ( ) V A V I
CE C
773 . 0 , 53 . 24 , =
Soln: The circuit shown is that of a
differential amplifier. We can use
superposition theorem to solve for
the output voltage: connect inputs
to ground (0 V), one at a time, and
solve for output voltage.

-

+
+

v
in
(t)

_
+

5V
_
+

v
o
(t)

_
R
2

5 k
V
a

V
b

Problem OP-AMP P1: - Consider the op-amp circuit shown below. If

() = 6 + 9(500), calculate the value of R
2
required to generate a
output, v
o
(t), with zero DC component. What is the resulting output
voltage?

From summing point constraints: V
a
= V
b

From KVL2
From KVL1 and Ohms law
Therefore

2 0
) ( 5 R t i v
in
=
O

=
k
v
i
in
in
5
5
( ) ( )
2
*
5
5 500 cos 9 6
5 R
k
t
v
o
O
+
=
t
i
in

KVL1
KVL2
-

+
+

v
in
(t)

_
+

5V
_
+

v
o
(t)

_
R
2

5 k V
a

V
b

If DC component of v
o
is zero,


Multiplying by 5kO on both sides and solving for R
2
,
R
2
= 25 k
Then the output is
o
= - 45(500),

( ) ( )
2
*
5
5 500 cos 9 6
5 R
k
t
v
o
O
+
=
t
2
*
5
5 6
5 0 R
kO

=
-

+
+

v
in
(t)

_
+

v
o
(t)

_
R
2

R
1

R
L

Soln: The full-power bandwidth of
the op-amp is given by


Slew-rate, SR = 1.5 V/s;
maximum output amplitude,V
om
= 12 V.
Problem OP-AMP P2: - Consider the op-amp circuit shown below. Assume
the maximum output voltage of the op-amp ranges from 12 V to + 12 V;
the maximum output current magnitude is 25 mA; and the slew-rate limit
is 1.5 V/s. If

()=

(), R
1
= 5 k, and R
2
= 25 k.

a) Find the full-power bandwidth of the op-amp.
om
FP
V
SR
f
t 2
=
kHz f
FP
9 . 19
) 12 ( 2
10 * 5 . 1
6
~ =
t
b) Find the peak output voltage possible without distortion for the following
cases:


Case a: Frequency of 5 kHz and R
L
= 20
Soln.: The current limit of the op-amp limits the peak output voltage.
Since R
L
is very small compared to R
2
the current through R
2
can be
neglected. Thus the peak output voltage is given by

Case b: Frequency of 5 kHz and R
L
= 2.5 k
Soln.: V
om
= 12 V (The maximum voltage that the op-amp can
achieve.)
Case c: Frequency of 50 kHz and R
L
= 2.5 k
Soln.: The slew-rate limit of the op-amp limits the peak output
voltage.




V
f
SR
V
om
7 . 4
) 10 * 50 ( 2
10 * 5 . 1
2
3
6
~ = =
t t
V R mA V
L om
5 . 0 * 25 = =
Soln:-
a) F(A, B, C) = (A + B)C + AC
F(A, B, C) = AC + BC + AC=
ABC+ABC+ABC+ABC+ABC





b) F(X, Y, Z) = (X + Y)(X + Z) + ZY
F(X, Y, Z) = XX + XZ + XY + YZ + ZY
F(X, Y, Z) = XZ + XY + YZ
= =XYZ+XYZ+XYZ+XYZ





Problem Logic Gates P1: - Express the following functions in canonical
SOP form. (Hint: Draw the truth table for each one first.).

A B C F
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
X Y Z F
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
c) F(A, B, C, D) = ABC + ABCD + ABCD + BD
F(A, B, C, D) =ABCD+ABCD+ ABCD + ABCD +
+ABCD+ABCD+ABCD
d) F(W, X, Y, Z) = WX + Z(Y + W) + WZY
F(W, X, Y, Z) = WX + YZ + WZ + WZY
F(W, X, Y, Z) = WXYZ+WXYZ+WXYZ+WXYZ+
+WXYZ+WXYZ+WXYZ+WXYZ+WXYZ

Karnaugh Map instead of truth table:
C
D
1 1
A 1 1 1
B
1 1
Y
Z
1 1
W 1 1 1 1
X 1
1 1
Soln. a:- Using NOR Gates





Soln. b:- Using NAND Gates









Problem Logic Gates P2: - Realize AND, OR and NOT functions
using: a) NOR, b) NAND

Soln:-
F = BCD + BCD + ACD + BCD + ABCD







SOP: F = BD + BC + AD








Problem Logic Gates P3: - a) Use Karnaugh-map to find the SOP
form of the following function:
F = BCD + BCD + ACD + BCD + ABCD

C
1 1
A
1 1 1
B
1 1 1
D
Soln:-
For minimum POS Minimize the logic function F and take
inverse. That is consider locations with zero (0) and then
invert the result.







POS: F = (B + D) . (A + B) . (C + D)








Problem Logic Gates P3: - b) Find the minimum POS form of the
function above and draw a logic circuit representing the same.
C
1 1 0 0
A
0 0 0 0
1 1 0 1
B
1 1 0 1
D