Virtual Addressing

Virtual Address to physical address translation

Use of TLB
DRAM technology
Each elementary DRAM cell is made up of a single MOS transistor and a
storage capacitor (fig1). Each storage cell contains one bit of information. This
charge, however, leaks off the capacitor due to the sub-threshold current of
the cell transistor. Therefore, the charge must be refreshed several times
each second.
DRAM technology
HOW THE DEVICE WORKS
The memory cell is written to by placing a 1 or 0 charge into the
capacitor cell. This is done during a write cycle by opening the cell transistor
(gate to power supply or VCC) and presenting either VCC or 0V (ground) at
the capacitor. The word line (gate of the transistor) is then held at ground to
isolate the capacitor charge. This capacitor will be accessed for either a new
write, a read, or a refresh.
DRAM technology
Simplified DRAM diagram
DRAM access diagram
The gates of the memory cells are tied to the rows. The read (or write) of a
DRAM is done in two main steps as illustrated in the fig below. The row (X)
and column (Y) addresses are presented on the same pads and
multiplexed. The first step consists of validating the row addresses and the
second step consists of validating the column addresses.
First Step: Row Addresses

Row addresses are present on address pads and are internally validated by the
RAS (Row Address Access) clock. The X addresses select one row through the row
decode, while all the other non-selected rows remain at 0V. Each cell of the
selected row is tied to a sense amplifier. A sense amplifier is a circuit that is able
to recognize if a charge has been loaded into the capacitor of the memory cell,
and to translate this charge or lack of charge into a 1 or 0. There are as many
sense amplifiers as there are cells on a row. Each sense amplifier is connected to
a column (Y address). In this first step all the cells of the entire row are read by
the sense amplifier. This step is long and critical because the row has a high time
constant due to the fact that it is formed by the gates of the memory cells. Also,
the sense amplifier has to read a very weak charge (approximately 30
femtoFarads or 30fF).

Second Step: Column Addresses

Following the first step, column addresses are present on the address pads and
are internally validated by the Column Address Access (CAS) clock. Each selected
memory cell has its data validated in a sense amplifier. Column access is fast. This
step consists of transferring data present in the sense amplifier to the Dout pin
through the column decode and the output buffer. On memory data sheets, the
access time from RAS is termed tRAC and the access time from CAS is listed as
tCAC. On a typical standard DRAM of 60ns access time, tRAC = 60ns and tCAC =
15ns.
Refresh

To maintain data integrity, it is necessary to refresh each DRAM memory cell.
Each row of cells is refreshed every cycle. For example, if the product
specification states, Refresh cycle = 512 cycles per 8ms, then there are 512
rows and each individual row must be refreshed every eight milliseconds.

As explained before, during the row access step, all the cells from the same
row are read by the sense amplifier. The sense amplifier has two roles. Since
it holds information within the cell, it is able to transmit this data to the
output buffer if it is selected by the column address. The sense amplifier is
also able to re-transmit (write) the information into the memory cell. In this
case, it refreshes the memory cell. When one row is selected, all the cells of
that row are read by the sense amplifiers and all these cells are refreshed one
at a time.
Current DRAM varieties
SRAM TECHNOLOGY
An SRAM (Static Random Access Memory) is designed to fill two needs: to
provide a direct interface with the CPU at speeds not attainable by DRAMs
and to replace DRAMs in systems that require very low power consumption.
In the first role, the SRAM serves as cache memory, interfacing between
DRAMs and the CPU.

The second driving force for SRAM technology is low power applications. In
this case, SRAMs are used in most portable equipment because the DRAM
refresh current is several orders of magnitude
more than the low-power SRAM standby current.
SRAM TECHNOLOGY
The SRAM cell consists of a bi-stable flip-flop connected to the internal
circuitry by two access transistors . When the cell is not addressed, the two
access transistors are closed and the data is kept to a stable state, latched
within the flip-flop.

The flip-flop needs the power supply to keep the information. The data in an
SRAM cell is volatile (i.e., the data is lost when the power is removed).
However, the data does not leak away like in a DRAM, so the SRAM does
not require a refresh cycle.
HOW THE DEVICE WORKS
Read/Write
To select a cell, the two access transistors
must be on so the elementary cell (the flip-
flop) can be connected to the internal SRAM
circuitry. These two access transistors of a cell
are connected to the word line (also called
row or X address). The selected row will be set
at VCC. The two flip-flop sides are thus
connected to a pair of lines, B and B. The bit
lines are also called columns or Y addresses.
During a read operation these two bit lines are
connected to the sense amplifier that
recognizes if a logic data 1 or 0 is stored in
the selected elementary cell. This sense
amplifier then transfers the logic state to the
output buffer which is connected to the output
pad. There are as many sense amplifiers as
there are output pads.
Read Operation
During a write operation, data comes from the
input pad. It then moves to the write circuitry.
Since the write circuitry drivers are stronger
than the cell flip-flop transistors, the data will
be forced onto the cell.


When the read/write operation is completed,
the word line (row) is set to 0V, the cell (flip-
flop) either keeps its original data for a read
cycle or stores the new data which was loaded
during the
write cycle.
Write Operation
Different types of SRAM cells are based on the type of load used in the
elementary inverter of the flip-flop cell. There are currently three types of SRAM
memory cells :

The 4T cell (four NMOS transistors plus two poly load resistors)
The 6T cell (six transistorsfour NMOS transistors plus two PMOS transistors)
The TFT cell (four NMOS transistors plus two loads called TFTs)
MEMORY CELL
6T Cell
This cell offers better electrical
performances (speed, noise immunity,
standby current) than a 4T structure.
The main disadvantage of this cell is its
large size.
Overview of SRAM Types
Logic Block Diagram
Cache Tag RAMs
The implementation of cache memory
requires the use of special circuits that
keep track of which data is in both the
SRAM cache memory and the main
memory (DRAM). This function acts like
a directory that tells the CPU what is or
is not in cache. The directory function
can be designed with standard logic
components plus small (and very fast)
SRAM chips for the data storage. An
alternative is the use of special memory
chips called cache tag RAMs, which
perform the entire function.