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Combinational Logic
Design&Analysis
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Introduction









We have learned all the prerequisite material:
Truth tables and Boolean expressions describe functions
Expressions can be converted into hardware circuits
Boolean algebra and K-maps help simplify expressions and circuits

Now, let us put all of these foundations to good use, to analyze and design
some larger circuits
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Introduction
Logic circuits for digital systems may be

Combinational
Sequential

A combinational circuit consists of logic gates whose outputs at any time
are determined by the current input values.

It has no memory elements No feedback from output to input

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Introduction
n binary inputs (n 1) 2^n possible input combinations

m binary outputs (m 1) - one possible binary value at the output for each
input combination => 2^n x m possible binary output values

m Bolean functions - each for an output

a timing specification consisting (at minimum) of an upper bound t
PD
on the
required time for the device to compute the specified output values from an
arbitrary set of stable, valid input values
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Design Procedure
The design of a combinational circuit involves the following steps:

Specification: How the circuit operates is clearly expressed

Formulation: Derivation of the truth table or the Boolean equations
that define the relationship between inputs and outputs

Optimization: Algebraic or K-map optimization of the truth table
and draw the corresponding logic diagram

Technology Mapping: Tranform the logic diagram to a new diagram
using the available implementation technology

Verification: Verify the correctness of the final design
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Comparing 2-bit Numbers - Specification
Lets design a circuit that compares two 2-bit numbers, A and B. The
circuit should have three outputs:

G (Greater) should be 1 only when A > B
E (Equal) should be 1 only when A = B
L (Lesser) should be 1 only when A < B

Make sure you understand the problem

Inputs A and B will be 00, 01, 10, or 11 (0, 1, 2 or 3 in decimal)
For any inputs A and B, exactly one of the three outputs will be 1
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Two 2-bit numbers means a total of four inputs

We should name each of them
Lets say the first number consists of digits A1 and A0 from left to
right, and the second number is B1 and B0

The problem specifies three outputs: G, E and L
Comparing 2-bit Numbers - Specification
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Comparing 2-bit Numbers - Formulation
For this problem, its probably easiest
to start with a truth table. This way,
we can explicitly show the relationship
(>, =, <) between inputs

A four-input function has a sixteen-
row truth table

Its usually clearest to put the truth
table rows in binary numeric order; in
this case, from 0000 to 1111 for A1,
A0, B1 and B0

Example: 01 < 10, so the sixth row of
the truth table (corresponding to
inputs A=01 and B=10) shows that
output L=1, while G and E are both 0.
A1 A0 B1 B0 G E L
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0 0 0 1
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

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A1 A0 B1 B0 G E L
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
Comparing 2-bit Numbers - Formulation
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Lets use K-maps. There are three functions (each with the same inputs
A1 A0 B1 B0), so we need three K-maps
G(A1,A0,B1,B0) =
A1 A0 B0 +
A0 B1 B0 +
A1 B1
E(A1,A0,B1,B0) =
A1 A0 B1 B0 +
A1 A0 B1 B0 +
A1 A0 B1 B0 +
A1 A0 B1 B0
L(A1,A0,B1,B0) =
A1 A0 B0 +
A0 B1 B0 +
A1 B1
B1
0 0 0 0
1 0 0 0
1 1 0 1
A0
A1
1 1 0 0
B0
B1
1 0 0 0
0 1 0 0
0 0 1 0
A0
A1
0 0 0 1
B0
B1
0 1 1 1
0 0 1 1
0 0 0 0
A0
A1
0 0 1 0
B0
Comparing 2-bit Numbers - Optimization
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Comparing 2-bit Numbers - Optimization
G = A1 A0 B0 + A0 B1 B0 + A1 B1
E = A1 A0 B1 B0 + A1 A0 B1 B0 + A1 A0 B1 B0 + A1 A0 B1 B0
L = A1 A0 B0 + A0 B1 B0 + A1 B1
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BCD-to-Excess-3 Code Converter - Specificaiton
The excess-3 code for a decimal digit is the binary combination corresponding
to the decimal digit plus 3. For example, the excess-3 code for decimal digit 5
is the binary combination for 5 + 3 = 8, which is 1000.

Each BCD digit is four bits with the bits, from most significant to least
significant, labeled A, B, C, D. Each excess-3 digit is four bits, with the bits,
from most significant to least significant, labeled W, X, Y, Z.
A
B
C
D
W
X
Y
Z
BCD
digit
Excess-3
digit
BCD-to
Excess-3
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BCD-to-Excess-3 Code Converter - Formulation
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BCD-to-Excess-3 Code Converter - Optimization
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BCD-to-Excess-3 Code Converter - Optimization
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BCD-to-Seven-Segment Decoder - Specification
Digital readouts found in many consumer electronic products often use Light
Emitting Diodes (LEDs). Each digit of the readout is formed from seven LED
segments. Each segment can be illuminated by a digital signal. A BCD-to-seven-
segment decoder is a combinational circuit that accepts a decimal digit in
BCD and generates the appropriate outputs for the segments of the display
for the decimal digit. The seven outputs of the decoder (a,b,c,d,e,f,g)
select the corresponding segments in the display. BCD-to-seven-segment
decoder has four inputs, A, B, C, and D for the BCD digit and seven outputs,
a through g, for controlling the segments.
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BCD-to-Seven-Segment Decoder - Formulation
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BCD-to-Seven-Segment Decoder - Optimization
a= AC + ABD + BCD + ABC

b= AB + ACD + ACD + ABC

c= AB + AD + BCD + ABC

d= AC^D + ABC + BCD + ABC + ABCD

e= ACD + BCD

f= ABC + ACD + ABD + ABC

g= ACD + ABC + ABC + ABC
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Divide and Conquer
A single very large-scale integrated (VLSI) processos circuit contains
several tens of millions of gates!

Imagine interconnecting these gates to form the processor

No complex circuit can be designed simply by interconnecting gates
one at a time

Divide and Conquer approach is used to deal with the complexity
System is usually partitioned into smaller parts which are further partitioned
This defines a hierarchy of design from complex to simple; top to bottom

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Divide and Conquer
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4-Bit Equality Comparator - Specification
The inputs to the circuit consist of two vectors: A(3:0) and B(3:0). Vector
A consists of four bits, A(3), A(2), A(1), and A(0), with A(3) as the
msb. Vector B consists of four bits, B(3), B(2), B(1), and B(0), with B(3) as
the msb. The output of the circuit is a single bit variable E. Output E
is equal to 1 if A and B are equal and equal to 0 if A and B are unequal.
4
4
A
B
E
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4-Bit Equality Comparator - Formulation
Since there are 8 inputs, using a truth table is impractical!!!

Apply divide and conquer design approach

Observation: In order for A and B to be equal, the bit values in each of
the respective positions, 3 down to 0, must be equal

We need four 1-bit comparator

We need an additional circuit to combine the outputs of 1-bit comparators
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4-Bit Equality Comparator - Optimization
A(i) B(i) E(i)
0 0 0
0 1 1
1 0 1
1 1 0
1-bit Comparator
E= (E(0) + E(1) + E(2) + E(3))
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4-Bit Equality Comparator - Optimization
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Techology Mapping NAND Gate Implementation
The circuit is defined in Sum-of-Products form

Goal: Use only NAND gates to implement the circuit

F= XY + XY + Z

F= (F)= [ (XY + XY + Z) ]

= [ (XY) . (XY) . (Z) ]
X
Y
Z
F
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Techology Mapping NOR Gate Implementation
The circuit is defined in Product-of-Sums form

Goal: Use only NOR gates to implement the circuit

F= (A + B)(C + D)E

F= (F)= [ { (A + B)(C + D)E } ]

= [ (A + B) + (C + D) + E ]
A
B
F
C
D
E
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Verification - Circuit Analysis
Circuit analysis involves figuring out what some circuit does

Every circuit computes some function, which can be described with
Boolean expressions or truth tables
So, the goal is to find an expression or truth table for the circuit

The first thing to do is to figure out what the inputs and outputs of the
overall circuit are
Inputs: x, y,z

Output: f
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Symbolic Analysis
We start with the circuit diagram
We determine gate output expressions
Intermediate expressions are combined in following gates to form
complex expressions
It might help to do some algebraic simplification along the way
We repeat until we have the output function and expression
Symbolic analysis gives both the truth table and logic expression
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Literal Analysis
Literal analysis is process of manually assigning a set of values to the
inputs, tracing the results, and recording the output values
For n inputs there are 2
n
possible input combinations
From input values, gate outputs are evaluated to form next set of
gate inputs
Evaluation continues until gate outputs are circuit outputs
Literal analysis only gives us the truth table
Once you know the number of inputs and outputs, list all the possible
input combinations in your truth table
A circuit with n inputs should have a truth table with 2
n
rows
x y z f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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Literal Analysis
You can simulate the circuit by hand to find the output for each possible
combination of inputs
x y z f
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1 1
1 1 0
1 1 1
1
0
1
1
0
0
1
1
0
1
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Literal Analysis
Doing the same thing for all the other input combinations yields the
complete truth table

This is simple, but tedious
x y z f
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
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Circuit Analysis
Remember that if you already have a Boolean expression, you can use that
to easily make a truth table

For example, since we already found that the circuit computes the function
f(x,y,z) = xz + yz + xyz, we can use that to fill in a table:
x y z xz yz xyz f
0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 0 0 1 1
0 1 1 0 0 0 0
1 0 0 0 0 0 0
1 0 1 1 1 0 1
1 1 0 0 0 0 0
1 1 1 1 0 0 1
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Circuit Analysis
The opposite is also true: its easy to come up with an expression
if you already have a truth table

Convert a truth table into a sum of minterms expression










You can then simplify this sum of minterms if desiredusing a K-map,
for example
x y z f
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
f(x,y,z) = xyz + xyz + xyz + xyz
= m
1
+ m
2
+ m
5
+ m
7

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Circuit Analysis Summary
After finding the circuit inputs and outputs, you can come up with either
an expression or a truth table to describe what the circuit does

You can easily convert between expressions and truth tables
Find the circuits
inputs and outputs
Find a Boolean
expression
for the circuit
Find a truth table
for the circuit