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    Interrupts in 8051: Microprocessor Laboratory EE-337

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    Ayandev Barman
    This document discusses interrupts in the 8051 microcontroller. It begins by defining an interrupt as a signal that notifies the processor it needs to service a device. When an interrupt occurs, the processor stops its current operation, saves context to the stack, and jumps to the interrupt service routine (ISR) address stored in the interrupt vector table. The 8051 has 5 interrupt sources - external hardware interrupts on pins 12 and 13, two timer interrupts, and a serial port interrupt. The document outlines the interrupt vector addresses and enabling interrupts using the IE register. It describes level-triggered and edge-triggered modes for the external hardware interrupts on pins 12 and 13.

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    Interrupts in 8051: Microprocessor Laboratory EE-337

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    Ayandev Barman
    86 views11 pages
    This document discusses interrupts in the 8051 microcontroller. It begins by defining an interrupt as a signal that notifies the processor it needs to service a device. When an interrupt occurs, the processor stops its current operation, saves context to the stack, and jumps to the interrupt service routine (ISR) address stored in the interrupt vector table. The 8051 has 5 interrupt sources - external hardware interrupts on pins 12 and 13, two timer interrupts, and a serial port interrupt. The document outlines the interrupt vector addresses and enabling interrupts using the IE register. It describes level-triggered and edge-triggered modes for the external hardware interrupts on pins 12 and 13.

    Original Description:

    8051 interrupt tutorial

    Original Title

    Interrupt

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    This document discusses interrupts in the 8051 microcontroller. It begins by defining an interrupt as a signal that notifies the processor it needs to service a device. When an interrupt occurs, the processor stops its current operation, saves context to the stack, and jumps to the interrupt service routine (ISR) address stored in the interrupt vector table. The 8051 has 5 interrupt sources - external hardware interrupts on pins 12 and 13, two timer interrupts, and a serial port interrupt. The document outlines the interrupt vector addresses and enabling interrupts using the IE register. It describes level-triggered and edge-triggered modes for the external hardware interrupts on pins 12 and 13.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    86 views11 pages

    Interrupts in 8051: Microprocessor Laboratory EE-337

    Uploaded by

    Ayandev Barman
    This document discusses interrupts in the 8051 microcontroller. It begins by defining an interrupt as a signal that notifies the processor it needs to service a device. When an interrupt occurs, the processor stops its current operation, saves context to the stack, and jumps to the interrupt service routine (ISR) address stored in the interrupt vector table. The 8051 has 5 interrupt sources - external hardware interrupts on pins 12 and 13, two timer interrupts, and a serial port interrupt. The document outlines the interrupt vector addresses and enabling interrupts using the IE register. It describes level-triggered and edge-triggered modes for the external hardware interrupts on pins 12 and 13.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 11

    Interrupts in 8051

    By Varun Patidar
    Ayandev Barman

    Microprocessor laboratory
    EE-337
    Introduction
    What is interrupt?
    An interrupt is a signal or notification to the processor/controller by hardware or
    software, which inform it that a device needs its service.



    Interrupt service routine
    Whenever there is interrupt invoked, the microcontroller/ microprocessor stops the
    current operation saves the location in stack and executes the Interrupt service routine.
    For every interrupt there is a fixed location in memory that the holds the address of its
    Interrupt service routine.
    Group of memory locations set aside to hold the addresses of ISR is called interrupt
    vector table.


    Interrupts in 8051
    There are mainly 5 interrupts in 8051.
    Interrupt vector table:









    *Note: If the service routine of a given interrupt is short enough to fit in the memory
    space(8 addresses) allotted to it, then its is placed in the vector table otherwise an LJMP
    instruction is placed in the vector table to point the address of the Interrupt service
    routine.

    Interrupt ROM location(Hex) Pin
    External hardware interrupt (INT0) 0003 P3.2(12)
    Timer 0 interrupt (TF0) 000B
    External hardware interrupt (INT0) 0013 P3.3(13)
    Timer 1 interrupt(TF1) 001B
    Serial COM interrupt (RI and TI) 0023
    Actions performed when interrupt arrives
    Finish the current instruction execution and save the address of the next instruction on
    the stack.
    Save the current status of all the interrupts internally.
    Jump to the fixed location as in Interrupt vector table which holds the address of the
    ISR.
    Jump to the address of ISR and start executing it until it reaches the last instruction of
    subroutine which is RETI
    After executing RETI, microcontroller returns to the place where it was interrupted and
    retrieves the PC(Program counter) address by popping last two bytes from the stack.
    Then it again resumes normal execution of instruction.
    How to enable or disable interrupt.
    There is a register called IE(interrupt enable) to
    disable or enable interrupt.
    D7 D0

    EA IE.7 Disables all interrupts
    -- IE.6 Not implemented, reserved for future use
    ET2 IE.5 Enables or disables timer 2 overflow or capture
    interrupt (8952)
    ES IE.4 Enables or disables the serial port interrupt
    ET1 IE.3 Enables or disables timer 1 overflow interrupt
    EX1 IE.2 Enables or disables external interrupt 1
    ET0 IE.1 Enables or disables timer 0 overflow interrupt
    EX0 IE.0 Enables or disables external interrupt 0

    *Note: To enable an interrupt Bit D7 of IE must be set to high.

    EA - ET2 ES ET1 EX1 ET0 EX0
    External hardware interrupt
    Pin 12 (INT0) and Pin 13(INT1) are designated as external hardware
    interrupts.
    Interrupt vector table location 0003H and 0013H are set aside for INT0 and
    INT1.


    There are 2 activation levels for external interrupts
    a) Level triggered
    b) Edge triggered
    Low-level triggered interrupt
    Pins P3.2 (INT0) and P3.3(INT1) are used for normal I/O unless the
    INT0 and INT1 bits in the IE register are enabled. After the hardware
    interrupts in the IE register are enabled, the controller keeps
    sampling the INTn pin for a low-level signal once each machine cycle.
    In this level triggered mode INT0 and INT1 are normally high and
    triggered on application of low-level signal.
    To ensure the activation of the hardware interrupt at the INTn pin,
    make sure that the duration of the low-level signal is around 4
    machine cycles, but no more.
    The low-level signal in the INT pin must be removed before the
    execution of last instruction RETI, otherwise another interrupt will
    be generated(i.e. ISR is executed again).

    Edge triggered interrupt
    INT0 and INT1 are normally low-level triggered interrupts.
    To make them edge-triggered interrupts, TCON register must be
    programmed. By setting bit D0 and D2 of TCON register, INT0 and
    INT1 are set as edge-triggered interrupt. Thus a falling edge of the
    signal applied at INT pins would now trigger ISR.
    The falling edge is latched by the 8051 and is held in TCON register
    (TCON.1 and TCON.3 bits), thus no new interrupt will be served until
    ISR is executed.
    In edge triggered interrupts external signal must be held high for
    atleast one machine cycle and then held low for atleast one machine
    cycle.


    TCON(Timer/Counter register)
    D7 D0

    TF1 TCON.7 Timer 1 overflow flag. Set by hardware when timer/counter 1 overflows
    Cleared by hardware as the
    TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
    Internal software interrupt

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