Data Flow Modeling

For complex designs.

Functional Implementation at a higher level
of abstraction.
Design in terms of the data flow between
registers.
RTL design for maximum flexibility.
(Register Transfer Level->dataflow modeling
+ behavioral modeling)
Dataflow modeling uses a number of operators that act
on operands to produce desired results.

Dataflow modeling uses continuous assignments and the
keyword assign.

A continuous assignment is a statement that assigns a
value to a net.

Continuous Assignments

Syntax:
assign #del <id> = <expr>;


Where to write them:
inside a module
outside procedures

Properties:
they all execute in parallel
are order independent
are continuously active
optional net type !!
Continuous assignment
o
Continuous assignment starts with keyword assign.
The left hand side of a continuous assignment command must be
a net-type signal.

The operands on the right-hand side can be registers or nets or
function calls.

Evaluation as soon as one of the right-hand-side operands changes
and the value is assigned to the left-hand-side net.

Ex.
a
b
c
x
AND
OR
module cir1 (o, a, b, c);
output o;
input a, b, c;
wire x;
assign x = a & b;
assign o = x | c;
endmodule
module cir1 (o, a, b, c);
output o;
input a, b, c;
wire x = a & b;
assign o = x | c;
endmodule
OR
Implicit Continuous Assignment
module cir1 (o, a, b, c);
output o;
input a, b, c;
assign x = a & b;
assign o = x | c;
endmodule
OR
Implicit Net Declaration
Regular Assignment Delay
assign #10 out = in1 & in2; // Delay in a continuous assign.
Implicit Continuous Assignment Delay
wire #10 out = in1 & in2;
same as wire out;
assign #10 out = in1 & in2;
Net Declaration Delay
wire # 10 out;
assign out = in1 & in2;
same as wire out;
assign #10 out = in1 & in2;
Adding delay to continuous assignment
Expressions, Operators, and Operands

Operators Operator Symbols Precedence
Unary + - ! ~ Highest precedence
Multiply, Divide, Modulus * / %
Add, Subtract + -
Shift << >>
Relational < <= > >=
Equality == != === !==
Reduction &, ~&

^ ^~

|, ~|
Logical &&

||
Conditional ?: Lowest precedence
Arithmetic operators
Available operators: +, -, *, /, % (modulo)
Arithmetic operators treat register operands as unsigned values
Example:
integer A;
A = -12;
A/4 -3
reg [7:0] A;
A = -12;
A/4 61
Relation and equality operators
Available relational operators: <, <=, >, >=
If any bit of an operand is X or Z, the result will be X
Available equality operators: ===, !==, ==, !=
= = =, != = : case equality (inequality). X and Z values are considered
in comparison
= =, != : logic equality (inequality). If any bit of an operand is
X or Z, the result will be X

X X 0 1 0XX0 0XX0
X X 1 0 0XX0 0110
0 1 0 1 0110 0110
!= == !== === Right Op. Left Op.
Example
Logic operators
Logic operators:
&& (logic and), || (logic or), ! (logic not)
Bit-wise logic operators:
& (and), | (or), ~ (not), ^ (xor), ~^ (xnor)
Reducation operators:
& (and), ~& (nand), | (or), ~| (nor), ^ (xor), ~^ (xnor)
0
^A
1 0 1 1 0 1010
~^A ~|A |A ~&A &A Operand A
1001
A^B
0110 0101 1011 0010 0011 1010
A~^B ~A A|B A&B Operand B Operand A
1 0 1 0 00 1010
0
!B
0 1 1 011 1010
!A A|B A&B Operand B Operand A
Shift operators
<< : shift left
>> : shift right
reg [3:0] A;
1 1 0 1 A << 2 0 1 0 0
zeros are moved in from the right end
reg [3:0] A;
1 1 0 1 A >> 2 0 0 1 1
Concatenation operators
Example
reg [7:0] A, B, Data;
reg c;

A = 10101101; B= 00110011;
c = 0;
Data = {A[3:0], B[7:6], c, c}; // Data = 11010000
1 1 0 1 0 0 0 0 Data
A[3:0] B[7:6]
c c
Replication Operator

For repetitive concatenation of the same number.

A replication constant specifies how many times to replicate
the number inside the brackets ( { } ).

A = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110;

Y = { 4{A} } // Result Y is 4'b1111

Y = { 4{A} , 2{B} } // Result Y is 8'b11110000

Y = { 4{A} , 2{B} , C } // Result Y is 10'b1111000010
Conditional Operator
The conditional operator(?:) is a ternary operator.
Usage: condition_expr ? true_expr : false_expr ;
Ex.2-to-1mux
assign out = control ? in1 : in0;

If the condition expression is x then true_expr and false_expr
are evaluated.

Results are compared, bit by bit, to return for each bit position
an x if the bits are different and the value of the bits if they are
the same.
EXAMPLES

//Dataflow description of 4-bit adder
module binary_adder (A,B,Cin,SUM,Cout);
input [3:0] A,B;
input Cin;
output [3:0] SUM;
output Cout;
assign {Cout,SUM} = A + B + Cin;
endmodule










//Dataflow description of 2-to-1-line multiplexer
module mux2_1_df (A,B,select,OUT);
input A,B,select;
output OUT;
assign OUT = select ? A : B; //(~select & B) | (select & A);
endmodule



4_1 mux?
Dataflow description of a 2-to-4-line decoder
module decoder_df (A,B,D);
input A,B;
output [3:0] D;
assign D[0] = ~A & ~B,
D[1] = ~A & B,
D[2] = A & ~B,
D[3] = A & B;
endmodule

assign D= (4b0001) << A; //input[1:0]A
A B D3 D2 D1 D0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Negative Edge-Triggered
D-flip flop with Clear
4-bit Ripple Carry Counter

module edge_dff(q, qbar, d, clk, clear);
output q,qbar;
input d, clk, clear;
wire s, sbar, r, rbar,cbar;
assign cbar = ~clear;
assign sbar = ~(rbar & s),
s = ~(sbar & cbar & ~clk),
r = ~(rbar & ~clk & s),
rbar = ~(r & cbar & d);
assign q = ~(s & qbar),
qbar = ~(q & r & cbar);
endmodule










module T_FF(q, clk, clear);
output q;
input clk, clear;
edge_dff ff1(q, ,~q, clk, clear);
endmodule

module counter (Q , clock, clear);
output [3:0] Q;
input clock, clear;
T_FF tff0(Q[0], clock, clear);
T_FF tff1(Q[1], Q[0], clear);
T_FF tff2(Q[2], Q[1], clear);
T_FF tff3(Q[3], Q[2], clear);
endmodule
module stimulus;
reg CLOCK, CLEAR;
wire [3:0] Q;
counter c1(Q, CLOCK, CLEAR);

initial $monitor($time, " Count Q = %b Clear= %b", Q[3:0],CLEAR);

initial
begin
CLEAR = 1'b1;
#34 CLEAR = 1'b0;
#200 CLEAR = 1'b1;
#50 CLEAR = 1'b0;
end

Initial
begin
CLOCK = 1'b0;
forever #10 CLOCK = ~CLOCK;
end

initial
begin
#400 $finish;
end
endmodule
0 Count Q = 0000 Clear= 1
34 Count Q = 0000 Clear= 0
40 Count Q = 0001 Clear= 0
60 Count Q = 0010 Clear= 0
80 Count Q = 0011 Clear= 0
100 Count Q = 0100 Clear= 0
120 Count Q = 0101 Clear= 0
140 Count Q = 0110 Clear= 0
160 Count Q = 0111 Clear= 0
180 Count Q = 1000 Clear= 0
200 Count Q = 1001 Clear= 0
220 Count Q = 1010 Clear= 0
234 Count Q = 0000 Clear= 1
284 Count Q = 0000 Clear= 0
300 Count Q = 0001 Clear= 0
320 Count Q = 0010 Clear= 0
340 Count Q = 0011 Clear= 0
360 Count Q = 0100 Clear= 0
380 Count Q = 0101 Clear= 0
output of the simulation