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PLL100

This document describes experiments performed with two PLL circuit trainer boards, the PLL100 and PLL02. The PLL100 experiment examines the capture range and lock range of a PLL circuit using an IC565 phase-locked loop. The PLL02 experiment investigates frequency synthesis by varying the division ratio of a PLL circuit containing IC4046 and IC4017 components to generate output frequencies from 1 kHz to 9 kHz. Procedures are outlined for connecting equipment like function generators, oscilloscopes, and frequency counters to observe input and output waveforms and measurements for both circuit boards.

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Oscar Tấn Xuân
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131 views25 pages

PLL100

This document describes experiments performed with two PLL circuit trainer boards, the PLL100 and PLL02. The PLL100 experiment examines the capture range and lock range of a PLL circuit using an IC565 phase-locked loop. The PLL02 experiment investigates frequency synthesis by varying the division ratio of a PLL circuit containing IC4046 and IC4017 components to generate output frequencies from 1 kHz to 9 kHz. Procedures are outlined for connecting equipment like function generators, oscilloscopes, and frequency counters to observe input and output waveforms and measurements for both circuit boards.

Uploaded by

Oscar Tấn Xuân
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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GROUP 4 PLL100-PLL02 08/05/2014 1

University Of Technical
Education HCM City

ELECTRONIC COMUNICATION
PRACTICE
Subject:
Instructor : Dang Phuoc Hai Trang
Group : 4

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 - PLL100 2
CHAPTER 1
PLL 100

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 3
I. INTRODUCTION:

PLL stands for 'Phase-Locked Loop' and is basically
a closed loop frequency control system, which
functioning is based on the phase sensitive
detection of phase difference between the input and
output signals of the controlled oscillator.

This trainer has been designed with a view to
provide practical and experimental knowledge of
Phase Lock Loop.

MODEL-PLL100 PLL02
GROUP 4 PLL100-PLL02
08/05/2014
4
II. IC 565:

- Frequency range:
0.001 Hz to 500 KHz.
- Voltage range: 6 V
to 12 V.
- Input level required
for tracking: 10mV
(rms) to 3V peak-to-
peak

MODEL-PLL100 PLL02
GROUP 4 PLL100-PLL02
08/05/2014
5
II. IC 565:

- Input impedance: 10k
- Output sink current:
1 mA.
- Output source current:
10 mA.
- Bandwidth adjustment
range : 1% to 60%.


MODEL-PLL100 PLL02
GROUP 4 PLL100-PLL02
08/05/2014
6
II. IC 565:

1 1
1.2
( )
4
OUT
f Hz
RC
=
1
2
3
2
(2. )(3.6)(10 )( )
L
C
f
f
C t
(
=
(


MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 7

MODEL-PLL100 PLL02
GROUP 4 PLL100-PLL02
08/05/2014
8
PLL100
III. PROCEDURE:

2. Connect sine wave signal form
external function generator at input
terminals. Connect CRO Channel-1
at input terminals. Keep amplitude at
10Vpp.
1. Connect Digital frequency counter
at the VCO O/P connector.
3. Connect CRO Channel-2 at VCO
output. Trigger CRO by channel-1.

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 9
PLL100
III. PROCEDURE:

4. Now vary frequency of input
sinewave generator from 8KHz to 16
KHz.
9KHz
10KHz
11,5KHz
12KHz
13KHz
14KHz
15KHz
16KHz


MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 10
PLL100
III. PROCEDURE:
5. Note down the instant frequency
when input and output signals
locked.This will be 12 KHz. Now vary
input frequency signal on both side of
12 KHz. The signals remain locked for
some range. Then signals become
unlock. Note down these
frequencies.The difference between
these frequencies is capture range.

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 11
PLL100
III. PROCEDURE:

6. Also note that once signals are
locked, both signals remain locked
for some range. This is lock range.

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 - PLL100 12
CHAPTER 2
PLL 02

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 13
I. INTRODUCTION:

This board has been designed with a view to
provide practical and experimental knowledge of
Frequency Synthesizer.

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 14
I. INTRODUCTION:

Phase/frequency
detector outputs
a signal that is
proportional to
the difference
between the
frequency/phase
of two input
periodic signals.

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 15
The low-pass
filter is use to
reduce the phase
noise and
enhance the
spectral purity of
the output.
I. INTRODUCTION:


MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 16
The voltage-
controlled
oscillator takes
the filtered
output of the
PFD and
generates an
output frequency
which is
controlled by the
applied voltage.
I. INTRODUCTION:


MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 17
I. INTRODUCTION:

The divider
scales the output
frequency by a
factor of N.

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 18
II. IC 4046 & 4017:

IC 4046:


MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 19
IC 4017:


MODEL-PLL100 PLL02
08/05/2014
GROUP 4 - PLL100 20

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 21
PLL-02
III. PROCEDURE:

1. Connect output of pulse generator
at input terminals.
2. Connect CRO Channel-1 at input
terminals. Also connect frequency
counter at these terminals.
3. Connect CRO Channel-2 at output
terminals. Also connect another frequency
counter at these terminals.

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 22
PLL-02
III. PROCEDURE:

4. Connect 1KHz output of Pulse
generator to input of synthesizer
circuit by jumper link. Connect
connector wire between Keep
1KHz-9KHz socket to X1 position.

5. Observe input and output
waveforms on CRO. Also observe
input and output frequencies on
frequency counters.

MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 23
PLL-02
III. PROCEDURE:

6. Both input and output frequencies
will be 1KHz frequency.
7. Now change position of jumper link
to X2 position. The output
frequency will be double of input
frequency.




MODEL-PLL100 PLL02
08/05/2014
GROUP 4 PLL100-PLL02 24
PLL-02
III. PROCEDURE:

8. Similarly observe other multiple
frequencies at output from 1KHz to
9KHz by changing jumper link switch
position to X3 to X9 positions.
- X3
- X4
- X5
- X6
- X7
- X8
- X9

08/05/2014
25 GROUP 4 PLL100-PLL02

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