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EE344 - Digital Systems Design

This document provides an overview of hardware descriptive language (HDL) and Verilog. It discusses why HDL is used instead of other languages, the evolution of computer-aided design tools, and different levels of abstraction in HDLs like Verilog. It also describes the Verilog design flow, common Verilog programming components like modules and instantiation, and port mapping in instantiation. The document is intended to introduce students to digital systems design using HDLs like Verilog.

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40 views20 pages

EE344 - Digital Systems Design

This document provides an overview of hardware descriptive language (HDL) and Verilog. It discusses why HDL is used instead of other languages, the evolution of computer-aided design tools, and different levels of abstraction in HDLs like Verilog. It also describes the Verilog design flow, common Verilog programming components like modules and instantiation, and port mapping in instantiation. The document is intended to introduce students to digital systems design using HDLs like Verilog.

Uploaded by

0307ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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EE344 DIGITAL

SYSTEMS DESIGN


REFERENCE:




Hardware Descriptive Language (HDL)
EE344 DIGITAL SYSTEMS DESIGN

September 2010

Abdullah Mansoor
Dept of Electrical Engineering
NUST School of Electrical Engineering and Computer Sciences (SEECS)
Outline
Why HDL?
Evolution of CAD and HDL
Abstraction and Level of Abstraction in HDL
Verilog Design Flow
Verilog Programming components
WHY HDL??
Hardware Descriptive Language
(HDL)
Why not C, C++, Java, Fortran or other
Higher level language??
Need true Hardware representation!


Concurrency
Evolution of Computer-Aided
Digital Design (CAD)
Very Large Scale Integration (VLSI)
More then 100,000 transistors Automated Design
Large Scale Integration
Thousands of Transistors Manual design
Medium Scale Integration
Few Hundreds of Transistors Manual design
Small Scale Integration (SSI)
Hundred Transistors Manual Design
Electronic Design Automation (EDA)
Verilog HDL
Developed at Automated Integrated Design
Systems in 1985 which is acquired by Cadence
in 1989.
The US Department of Defense developed
VHDL (VHSIC HDL) as open source
Cadence opened Verilog to the public in 1990
afraid of losing market share.
IEEE defined standard for Verilog (IEEE 1364-
2001)
Abstraction
Mean identifying aspects that are
important to a task at hand, and hiding
details of other aspects
Example Logic Levels: 0 or 1
Real Word Circuits

Representation of Real World Circuits
Logic Levels
Capacitive Load and Propagation Delay
Power
Ref: Ch1 Ashenden
Book
Verilog Levels of Abstraction
Behavioral/Algorithmic Level
Describes a system by sequential algorithms.
Register Transfer Level (RTL)
Here we specify the characteristics of circuits by
operations and the transfer of data between the
registers
Structural/Gate Level
Here you define the circuit in terms of its connection
of building block e.g defining NAND gate in terms of
AND and NOT

Behavioral level of Abstraction
Example Representation of
MUX using If-else statements

If (S==0) then
Y = I
0
else
Y =I
1
end
Maximum
level of
Abstraction
Programming
at this level is
similar to
programming
in C.
Implementation
of algorithms
using if-else
and similar
constructs
Structural level of Abstraction

Minimum
level of
Abstraction
Register Transfer Level
(RTL) of Abstraction
Implementation of shifters using Flip Flop
circuits instead of using operators
Medium
level of
Abstraction
Verilog Design Flow
Design Entry
Functional Verification
Synthesis
Pos-Synthesis Verification
Physical Implementation
Physical Verification
Module in Verilog
A module defines the input and output of a block and its operation
either in terms of behavioral style or structural style
Its like function definition in C but there is no return call unlike C
General Module style:
module <NAME> (<LIST OF PORTS>);
<declaration & implementation>
endmodule
Example
module and (a, b, out);
input a, b;
output out;
out=a&b;
endmodule

Instantiation of Modules
Instantiation
Instantiation helps re-using pre-defined modules
Instantiation defines hierarchy of the design
Example of a system with multiple MUX
Syntax for Instantiation:
<Buit-in gates or predefined Modules>
<instance_name>(interconnections;output is first then
inputs);
Example:
and A1 (Y, A, B);

Port Mapping in Instantiation
It is the association of ports between
instantiated module and the predefined
module.
There are two types
In the next lecture you will
learn
More detail about code synthesis
Test Bench: to test your circuit
Data types and variables


Reading Assignment: Chapter 1& 2
PALNITKAR BOOK
Thank you!

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