Prepared by: Ankur Changela
Fan-In
Fan-in is the number of inputs a gate can handle.
Physical logic gates with a large fan-in tend to be slower than those
with a small fan-in, because the complexity of the input circuitry
increases the input capacitance of the device.
Fan-Out
The maximum number of standard logic inputs that an output can
drive reliably.
Also known as the loading factor.
Fan-In & Fan-Out
t
pLH
: delay time in going from logical 0 to logical 1 state (LOW to HIGH)
t
pHL
: delay time in going from logical 1 to logical 0 state (HIGH to LOW)
Measured at 50%
points.
Trise and Tfall
Propagation Delays
Every IC needs a certain amount of electrical power to
operate.
V
cc
(TTL)
V
DD
(MOS)
Power dissipation determined by I
cc
and V
cc
.
Average I
cc
(avg)= (I
CCH
+ I
CCL
)/2
P
D
(avg) = I
cc
(avg) x V
cc
Power Requirements
L d d
L
d d
L
d
d
L
VccCV t P
Ic
CV
VccIc t P
Ic
CV
t
t
V
C
dt
dv
C Ic
Pd *td=Vcc*C*VL
Lets take an Example of 1Watt Packaging..
C = 50 fF, Vcc = 3v, VL =0.5V
Case 1 td = 1 ns Find out the no of gates that can be accommodated to Packege.
Case 2 gates /packege
Find out the delays.
There is always compromise between Power Dissipation & Delay
Power Delay Product
5
10
IDEAL INVERTER VOLTAGE TRANSFER
CHARTERISTIC (VTC)
Actual Inverter Characteristics
VOH -> max output voltage when output is 1
VOL -> min output voltage when output is 0
VIL ->max i/p voltage which can be interpreted as 0
VIH ->min input voltage which can be interpreted as 1
NOISE IMMUNITY AND NOISE MARGINS
What happens if noise causes the input voltage to drop
below V
IH
(min) or rise above V
IL
(max)?
The noise immunity of a logic circuit refers to the circuits
ability to tolerate noise without causing spurious changes
in the output voltage.
Noise margin: Figure 8-4.
V
NH
=V
OH
(min)-V
IH
(min)
V
NL
=V
IL
(max)-V
OL
(max)
Example 8-1.
Noise Immunity
Figure 8-4: Noise Margin
Figure 8-1
Current-Sourcing and Sinking
DIODE LOGIC
Reverse Bias
A B Y
H H H
DIODE LOGIC
Reverse Bias
Forward Bias
A B Y
H L L
DIODE LOGIC
Forward Bias
Reverse Bias
A B Y
L H L
DIODE LOGIC
Forward Bias
Forward Bias
A B Y
L L L
DIODE LOGIC
A B Y
L L L
L H L
H L L
H H H
DTL
DTL
0.2 V
Vp=0.9 V
0.7 V
5 V
Reverse Bias
Forward Bias
Saturation
Ic
All volt drops across the R
LOW
DTL
0.2 V
Vp=0.9 V
0.7 V
5 V
Reverse Bias
Forward Bias
Cut-off
Ic=0
VR = 0v
HIGH
0.45 V
DTL
When transistor switches from satn
to cut-off, excess charge from the
base (reverse base current)has to be
removed.
Switching Problem
There is no any mechanism
for this reverse base current
to flow
DTL
5 V
5 V
Part of the IB
flows through
this
Dual Power Supply
TTL
0.2 V
5 V
Vp=0.9 V
IB =5-0.9/4 =1 mA
4K
0.2 V
Emitter Current flows
TTL
5 V
5 V
Vp=1.4 V
4K
0.2 V
Base Emitter in R.B
Base Collector in F.B
Transistor in reverse
active mode
In reverse mode collector & emitter
terminal are interchanged and is
very small around 0.02
5 V
0.2 V
Emitter Current flows
T2 goes off
T3 goes off as base current
is supplied by IE of T2
base current is
supplied by Vcc
through 1.4k and
T4 goes on
5 V
5 V
Emitter Current flows
T2 goes on
T3 goes on as base current
is supplied by IE of T2
?
5 V
5 V
Emitter Current flows
T2 goes on
T3 goes on as base current
is supplied by IE of T2
Vp3-Vp1=0.7 will be
shared by two
diodes
Vp1=0.2 V
Vp2=0.7 V
Vp3=0.9 V
